HomeSort by: relevance | last modified time | path
    Searched refs:SPLL_RESET (Results 1 - 20 of 20) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
rv740d.h 29 #define SPLL_RESET (1 << 0)
rv730d.h 29 #define SPLL_RESET (1 << 0)
rs780d.h 29 # define SPLL_RESET (1 << 0)
radeon_rv740_dpm.c 373 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
radeon_rv730_dpm.c 295 spll_func_cntl |= SPLL_RESET | SPLL_BYPASS_EN;
rv770d.h 92 #define SPLL_RESET (1 << 0)
nid.h 541 #define SPLL_RESET (1 << 0)
cikd.h 251 #define SPLL_RESET (1 << 0)
sid.h 88 #define SPLL_RESET (1 << 0)
evergreend.h 77 #define SPLL_RESET (1 << 0)
r600d.h 1273 # define SPLL_RESET (1 << 0)
radeon_cypress_dpm.c 1434 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
radeon_rv770_dpm.c 981 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
radeon_ci_dpm.c 3029 spll_func_cntl |= SPLL_RESET;
radeon_si.c 4030 tmp |= SPLL_RESET;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h 90 #define SPLL_RESET (1 << 0)
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 1353 SPLL_RESET, 1);
amdgpu_iceland_smumgr.c 1469 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
amdgpu_ci_smumgr.c 1421 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
amdgpu_tonga_smumgr.c 1218 SPLL_RESET, 1);

Completed in 112 milliseconds