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Searched refs:UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK (Results 1 - 15 of 15) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v5_0.c	`665 data \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK \| 752 data \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 761 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 829 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)`
amdgpu_uvd_v4_2.c	`592 data \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 601 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 616 tmp \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK \|`
amdgpu_uvd_v6_0.c	`1320 data \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK \| 1410 data \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 1419 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 1492 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)`
amdgpu_uvd_v7_0.c	`852 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0); 965 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK); 1605 data \|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK \|`
amdgpu_vcn_v1_0.c	`469 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;`
amdgpu_vcn_v2_0.c	`463 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;`
amdgpu_vcn_v2_5.c	`550 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h	`38 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L`
uvd_4_2_sh_mask.h	`223 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1`
uvd_5_0_sh_mask.h	`243 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1`
uvd_6_0_sh_mask.h	`245 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1`
uvd_7_0_sh_mask.h	`443 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`936 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L`
vcn_2_0_0_sh_mask.h	`1955 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L`
vcn_2_5_sh_mask.h	`2004 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L`

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