HomeSort by: relevance | last modified time | path
    Searched refs:UVD_CGC_CTRL__REGS_MODE_MASK (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c 507 | UVD_CGC_CTRL__REGS_MODE_MASK
608 | UVD_CGC_CTRL__REGS_MODE_MASK
666 UVD_CGC_CTRL__REGS_MODE_MASK |
amdgpu_vcn_v2_0.c 500 | UVD_CGC_CTRL__REGS_MODE_MASK
576 UVD_CGC_CTRL__REGS_MODE_MASK |
635 | UVD_CGC_CTRL__REGS_MODE_MASK
amdgpu_vcn_v2_5.c 590 | UVD_CGC_CTRL__REGS_MODE_MASK
667 UVD_CGC_CTRL__REGS_MODE_MASK |
729 | UVD_CGC_CTRL__REGS_MODE_MASK
amdgpu_uvd_v5_0.c 677 UVD_CGC_CTRL__REGS_MODE_MASK |
amdgpu_uvd_v6_0.c 1332 UVD_CGC_CTRL__REGS_MODE_MASK |
amdgpu_uvd_v7_0.c 1617 UVD_CGC_CTRL__REGS_MODE_MASK |
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h 58 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L
uvd_4_2_sh_mask.h 245 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000
uvd_5_0_sh_mask.h 267 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000
uvd_6_0_sh_mask.h 269 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000
uvd_7_0_sh_mask.h 454 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h 947 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L
vcn_2_0_0_sh_mask.h 1966 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L
vcn_2_5_sh_mask.h 2015 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L

Completed in 88 milliseconds