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Searched refs:UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK (Results 1 - 5 of 5) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_jpeg_v1_0.c	`526 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 531 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);`
amdgpu_vcn_v1_0.c	`1308 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1316 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`732 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L`
vcn_2_0_0_sh_mask.h	`707 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L`
vcn_2_5_sh_mask.h	`710 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L`

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