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Searched refs:UVD_SUVD_CGC_CTRL__SRE_MODE_MASK (Results 1 - 12 of 12) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v5_0.c	`690 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK \|`
amdgpu_vcn_v1_0.c	`550 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 623 data \|= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK`
amdgpu_vcn_v2_0.c	`543 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 650 data \|= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK`
amdgpu_vcn_v2_5.c	`633 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 743 data \|= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK`
amdgpu_uvd_v6_0.c	`1346 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK \|`
amdgpu_uvd_v7_0.c	`1631 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK \|`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_5_0_sh_mask.h	`787 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1`
uvd_6_0_sh_mask.h	`781 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1`
uvd_7_0_sh_mask.h	`257 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`549 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L`
vcn_2_0_0_sh_mask.h	`3308 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L`
vcn_2_5_sh_mask.h	`2182 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L`

Completed in 81 milliseconds