| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_trinity_smc.c | 71 WREG32_SMC(SMU_SCRATCH0, 1);
73 WREG32_SMC(SMU_SCRATCH0, 0);
80 WREG32_SMC(SMU_SCRATCH0, n);
87 WREG32_SMC(SMU_SCRATCH0, n);
|
| radeon_ci_smc.c | 124 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
132 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
148 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
157 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
|
| radeon_si_smc.c | 124 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
138 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
154 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
163 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
|
| radeon_trinity_dpm.c | 388 WREG32_SMC(GFX_POWER_GATING_CNTL, value);
512 WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01));
530 WREG32_SMC(PM_I_CNTL_1, value);
535 WREG32_SMC(SMU_S_PG_CNTL, value);
539 WREG32_SMC(SMU_S_PG_CNTL, value);
543 WREG32_SMC(PM_I_CNTL_1, value);
604 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
614 WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value);
626 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
638 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value)
[all...] |
| radeon_ci_dpm.c | 604 WREG32_SMC(config_regs->offset, data);
894 WREG32_SMC(CG_THERMAL_INT, tmp);
901 WREG32_SMC(CG_THERMAL_CTRL, tmp);
918 WREG32_SMC(CG_THERMAL_INT, thermal_int);
927 WREG32_SMC(CG_THERMAL_INT, thermal_int);
954 WREG32_SMC(CG_FDO_CTRL2, tmp);
958 WREG32_SMC(CG_FDO_CTRL2, tmp);
1132 WREG32_SMC(CG_FDO_CTRL0, tmp);
1209 WREG32_SMC(CG_TACH_CTRL, tmp);
1225 WREG32_SMC(CG_FDO_CTRL2, tmp)
[all...] |
| radeon_kv_dpm.c | 281 WREG32_SMC(local_cac_reg->cntl, data);
321 WREG32_SMC(config_regs->offset, data);
412 WREG32_SMC(LCAC_SX0_OVR_SEL, 0);
413 WREG32_SMC(LCAC_SX0_OVR_VAL, 0);
416 WREG32_SMC(LCAC_MC0_OVR_SEL, 0);
417 WREG32_SMC(LCAC_MC0_OVR_VAL, 0);
420 WREG32_SMC(LCAC_MC1_OVR_SEL, 0);
421 WREG32_SMC(LCAC_MC1_OVR_VAL, 0);
424 WREG32_SMC(LCAC_MC2_OVR_SEL, 0);
425 WREG32_SMC(LCAC_MC2_OVR_VAL, 0)
[all...] |
| radeon_cik.c | 9505 WREG32_SMC(cntl_reg, tmp);
9552 WREG32_SMC(CG_ECLK_CNTL, tmp);
9851 WREG32_SMC(THM_CLK_CNTL, data);
9857 WREG32_SMC(MISC_CLK_CTRL, data);
9862 WREG32_SMC(CG_CLKPIN_CNTL, data);
9867 WREG32_SMC(CG_CLKPIN_CNTL_2, data);
9873 WREG32_SMC(MPLL_BYPASSCLK_SEL, data);
|
| radeon_si.c | 5473 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0);
5474 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0);
5485 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff);
5486 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff);
|
| radeon.h | 2608 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2642 WREG32_SMC(reg, tmp_); \
|
| radeon_si_dpm.c | 2770 WREG32_SMC(offset, data);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_si_smc.c | 122 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
136 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
155 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
|
| amdgpu_kv_dpm.c | 408 WREG32_SMC(local_cac_reg->cntl, data);
448 WREG32_SMC(config_regs->offset, data);
539 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
540 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
543 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
544 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
547 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
548 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
551 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
552 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0)
[all...] |
| amdgpu_vi.c | 412 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
423 WREG32_SMC(ixROM_CNTL, rom_cntl);
811 WREG32_SMC(cntl_reg, tmp);
901 WREG32_SMC(reg_ctrl, tmp);
1507 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
|
| amdgpu_cik.c | 928 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
939 WREG32_SMC(ixROM_CNTL, rom_cntl);
1400 WREG32_SMC(cntl_reg, tmp);
1449 WREG32_SMC(ixCG_ECLK_CNTL, tmp);
1760 WREG32_SMC(ixTHM_CLK_CNTL, data);
1768 WREG32_SMC(ixMISC_CLK_CTRL, data);
1773 WREG32_SMC(ixCG_CLKPIN_CNTL, data);
1778 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data);
1784 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data);
|
| amdgpu_cgs.c | 103 return WREG32_SMC(index, value);
|
| amdgpu_debugfs.c | 517 WREG32_SMC(*pos, value);
|
| amdgpu_vce_v4_0.c | 890 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
|
| amdgpu.h | 1069 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
|
| amdgpu_uvd_v7_0.c | 1696 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
|
| amdgpu_si_dpm.c | 2870 WREG32_SMC(offset, data);
7524 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7529 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7541 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7546 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
|
| amdgpu_gfx_v8_0.c | 801 WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
|
