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Searched refs:YCLK_POST_DIV_MASK (Results 1 - 14 of 14) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
rv740d.h	`55 #define YCLK_POST_DIV_MASK (3 << 17)`
radeon_rv740_dpm.c	`217 YCLK_POST_DIV_MASK \| 234 YCLK_POST_DIV_MASK \|`
rv770d.h	`128 #define YCLK_POST_DIV_MASK (3 << 17)`
radeon_cypress_dpm.c	`521 YCLK_POST_DIV_MASK \| 538 YCLK_POST_DIV_MASK \|`
radeon_rv770_dpm.c	`433 YCLK_POST_DIV_MASK \| 461 YCLK_POST_DIV_MASK \|`
nid.h	`570 #define YCLK_POST_DIV_MASK (3 << 17)`
cikd.h	`750 #define YCLK_POST_DIV_MASK (7 << 0)`
sid.h	`627 #define YCLK_POST_DIV_MASK (7 << 0)`
evergreend.h	`108 #define YCLK_POST_DIV_MASK (3 << 17)`
radeon_ni_dpm.c	`2202 YCLK_POST_DIV_MASK \| 2219 YCLK_POST_DIV_MASK \|`
radeon_ci_dpm.c	`2824 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 2828 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK \| YCLK_POST_DIV_MASK);`
radeon_si_dpm.c	`4908 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4912 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK \| YCLK_POST_DIV_MASK);`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h	`629 #define YCLK_POST_DIV_MASK (7 << 0)`
amdgpu_si_dpm.c	`5372 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 5376 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK \| YCLK_POST_DIV_MASK);`

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