| /src/sys/arch/mmeye/stand/boot/ |
| clock.c | 51 t1 = _reg_read_4(SH_(TCNT0));
53 t2 = _reg_read_4(SH_(TCNT0));
|
| /src/sys/arch/hpc/stand/hpcboot/sh3/ |
| sh_mmu.cpp | 56 asid = _reg_read_4(SH3_PTEH) & SH3_PTEH_ASID_MASK;
63 dum = _reg_read_4(vaddr);
69 aae = _reg_read_4(SH3_MMUAA | entry_idx);
78 dae = _reg_read_4(SH3_MMUDA | entry_idx);
108 r = _reg_read_4(SH3_CCR);
118 r = _reg_read_4(SH4_CCR);
161 r = _reg_read_4(SH3_MMUCR);
181 r = _reg_read_4(SH3_MMUAA | a);
185 r = _reg_read_4(SH3_MMUDA | a);
200 r = _reg_read_4(SH4_MMUCR)
[all...] |
| /src/sys/arch/playstation2/ee/ |
| dmac.c | 97 if (_reg_read_4(D_STAT_REG) & D_STAT_SIM)
99 if (_reg_read_4(D_STAT_REG) & D_STAT_MEIM)
103 _reg_write_4(D_STAT_REG, _reg_read_4(D_STAT_REG) & D_STAT_CIS_MASK);
119 r = _reg_read_4(D_STAT_REG);
167 _reg_write_4(D_STAT_REG, (_reg_read_4(D_STAT_REG) & mask) ^ mask);
175 _reg_write_4(D_STAT_REG, _reg_read_4(D_STAT_REG) & D_STAT_CIM_BIT(ch));
184 cur_mask = _reg_read_4(D_STAT_REG);
273 r = _reg_read_4(D_ENABLER_REG);
277 _reg_write_4(chcr, (_reg_read_4(chcr) | D_CHCR_STR));
293 r = _reg_read_4(D_ENABLER_REG)
[all...] |
| intc.c | 78 _reg_write_4(I_STAT_REG, _reg_read_4(I_STAT_REG));
90 r = _reg_read_4(I_STAT_REG);
136 _reg_write_4(I_MASK_REG, (_reg_read_4(I_MASK_REG) & mask) ^ mask);
144 _reg_write_4(I_MASK_REG, _reg_read_4(I_MASK_REG) & (1 << ch));
152 cur_mask = _reg_read_4(I_MASK_REG);
|
| eevar.h | 43 #define _reg_read_4(a) __read_4(a) macro
|
| timer.c | 103 _reg_write_4(T0_MODE_REG, _reg_read_4(T0_MODE_REG) | T_MODE_EQUF);
|
| /src/sys/arch/sh3/sh3/ |
| pmb.c | 55 pascr = _reg_read_4(ST40_PASCR);
67 uint32_t mmucr = _reg_read_4(SH4_MMUCR);
106 uint32_t addr = _reg_read_4(ST40_PMB_AA + offset);
111 uint32_t data = _reg_read_4(ST40_PMB_DA + offset);
|
| mmu.c | 84 r = _reg_read_4(SH3_MMUCR);
95 r = _reg_read_4(SH4_MMUCR);
|
| mmu_sh4.c | 99 opteh = _reg_read_4(SH4_PTEH); /* save current ASID */
116 uint32_t aa = _reg_read_4(addr);
123 uint32_t aa = _reg_read_4(addr);
178 limit = _reg_read_4(SH4_MMUCR) & SH4_MMUCR_URB_MASK;
202 opteh = _reg_read_4(SH4_PTEH); /* save old ASID */
|
| db_interface.c | 282 r = _reg_read_4(SH3_MMUCR);
287 i = _reg_read_4(SH3_PTEH) & SH3_PTEH_ASID_MASK;
299 r = _reg_read_4(SH3_MMUAA | a);
312 r = _reg_read_4(SH3_MMUDA | a);
338 r = _reg_read_4(SH4_MMUCR);
345 i = _reg_read_4(SH4_PTEH) & SH4_PTEH_ASID_MASK;
410 *paa = _reg_read_4(SH4_ITLB_AA | e);
411 *pda1 = _reg_read_4(SH4_ITLB_DA1 | e);
412 *pda2 = _reg_read_4(SH4_ITLB_DA2 | e);
420 *paa = _reg_read_4(SH4_UTLB_AA | e)
[all...] |
| mmu_sh3.c | 88 if ((_reg_read_4(aa) & SH3_MMUAA_D_ASID_MASK) == asid)
111 entry = _reg_read_4(aa)
173 entry = _reg_read_4(SH3_MMUAA | a);
|
| interrupt.c | 391 printf("INTEVT=0x%x", _reg_read_4(SH_(INTEVT)));
395 printf(" INTEVT2=0x%x", _reg_read_4(SH7709_INTEVT2));
458 r = _reg_read_4(iprreg);
|
| clock.c | 109 (0xffffffff - _reg_read_4(SH_(TCNT ## x)))
213 return 0xffffffff - _reg_read_4(SH_(TCNT2));
|
| /src/sys/arch/hpc/stand/hpcboot/sh3/cpu/ |
| 7709.h | 54 _reg_read_4(__a) &= ~0x3; /* Clear U,V bit */ \
|
| 7709a.h | 54 _reg_read_4(__a) &= ~0x3; /* Clear U,V bit */ \
|
| 7707.h | 65 _reg_read_4(__a) &= ~0x3; /* Clear U,V bit */ \
|
| /src/sys/arch/evbsh3/ap_ms104_sh4/ |
| ap_ms104_sh4.c | 76 reg = _reg_read_4(SH4_PCTRA);
95 KASSERT((_reg_read_4(SH4_PCTRA) & (1 << (pin * 2))) == 0); /*input*/
148 reg = _reg_read_4(SH4_PCTRA);
|
| rs5c316_mainbus.c | 95 reg = _reg_read_4(SH4_PCTRA);
148 reg = _reg_read_4(SH4_PCTRA);
|
| /src/sys/arch/playstation2/playstation2/ |
| interrupt.c | 279 (_reg_read_4(I_MASK_REG) << 16) |
280 (_reg_read_4(I_STAT_REG) & 0x0000ffff),
281 _reg_read_4(D_STAT_REG));
|
| /src/sys/arch/sh3/include/ |
| devreg.h | 40 #define _reg_read_4(a) (*(volatile uint32_t *)((vaddr_t)(a))) macro
|
| /src/sys/arch/landisk/stand/boot/ |
| delay.c | 118 return ~(_reg_read_4(TCNT));
|
| /src/sys/arch/sh3/dev/ |
| shpcic.c | 98 id = _reg_read_4(SH4_PCICONF0);
135 id = _reg_read_4(SH4_PCICONF0);
136 class = _reg_read_4(SH4_PCICONF2);
141 _reg_write_4(SH4_BCR1, _reg_read_4(SH4_BCR1) | BCR1_BREQEN);
156 _reg_write_4(SH4_PCIBCR1, _reg_read_4(SH4_BCR1) | BCR1_MASTER);
175 _reg_write_4(SH4_PCIWCR1, _reg_read_4(SH4_WCR1));
180 _reg_write_4(SH4_PCIWCR2, _reg_read_4(SH4_WCR2));
185 _reg_write_4(SH4_PCIWCR3, _reg_read_4(SH4_WCR3));
190 _reg_write_4(SH4_PCIMCR, _reg_read_4(SH4_MCR));
297 data = _reg_read_4(SH4_PCIPDR)
[all...] |
| /src/sys/arch/evbsh3/evbsh3/ |
| machdep.c | 542 evtcode = _reg_read_4(SH3_INTEVT);
547 evtcode = _reg_read_4(SH7709_INTEVT2);
554 evtcode = _reg_read_4(SH4_INTEVT);
|
| /src/sys/arch/hpc/stand/hpcboot/ |
| hpcboot.h | 126 #define _reg_read_4(a) (*(volatile uint32_t *)(a)) macro
|
| /src/sys/arch/hpc/stand/hpcboot/sh3/dev/ |
| sh4_dev.cpp | 120 bitdisp(_reg_read_4(SH4_INTEVT));
|
