Searched refs:adev (Results 1 - 25 of 321) sorted by relevance

1234567891011>>

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_debugfs.h36 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
37 void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
38 int amdgpu_debugfs_init(struct amdgpu_device *adev);
39 void amdgpu_debugfs_preempt_cleanup(struct amdgpu_device *adev);
40 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
43 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
44 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
45 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev);
H A Dgfxhub_v2_0.h29 u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev);
30 int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev);
31 void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev);
32 void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
34 void gfxhub_v2_0_init(struct amdgpu_device *adev);
35 u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev);
36 void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
H A Dmmhub_v2_0.h28 int mmhub_v2_0_gart_enable(struct amdgpu_device *adev);
29 void mmhub_v2_0_gart_disable(struct amdgpu_device *adev);
30 void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
32 void mmhub_v2_0_init(struct amdgpu_device *adev);
33 int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
35 void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags);
36 void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
H A Damdgpu_atomfirmware.h31 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev);
32 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
33 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
34 int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
36 int amdgpu_atomfirmware_get_mem_train_info(struct amdgpu_device *adev);
37 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
38 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev);
39 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev);
40 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev);
H A Dgfx_v9_4.h29 void gfx_v9_4_clear_ras_edc_counter(struct amdgpu_device *adev);
31 int gfx_v9_4_query_ras_error_count(struct amdgpu_device *adev,
34 int gfx_v9_4_ras_error_inject(struct amdgpu_device *adev,
H A Damdgpu_display.h28 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
29 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
30 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
31 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (
[all...]
H A Dgfxhub_v1_1.h29 int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev);
H A Damdgpu_pm.h38 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
39 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev);
40 int amdgpu_pm_virt_sysfs_init(struct amdgpu_device *adev);
41 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev);
42 void amdgpu_pm_virt_sysfs_fini(struct amdgpu_device *adev);
43 void amdgpu_pm_print_power_states(struct amdgpu_device *adev);
44 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version);
45 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev);
47 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
48 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, boo
[all...]
H A Dmmhub_v9_4.h30 u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev);
31 int mmhub_v9_4_gart_enable(struct amdgpu_device *adev);
32 void mmhub_v9_4_gart_disable(struct amdgpu_device *adev);
33 void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev,
35 void mmhub_v9_4_init(struct amdgpu_device *adev);
36 int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
38 void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags);
39 void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
H A Dgfxhub_v1_0.h29 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev);
30 void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev);
31 void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
33 void gfxhub_v1_0_init(struct amdgpu_device *adev);
34 u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev);
35 void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
H A Damdgpu_vf_error.c33 void amdgpu_vf_error_put(struct amdgpu_device *adev, argument
41 if (!amdgpu_sriov_vf(adev))
46 mutex_lock(&adev->virt.vf_errors.lock);
47 index = adev->virt.vf_errors.write_count % AMDGPU_VF_ERROR_ENTRY_SIZE;
48 adev->virt.vf_errors.code [index] = error_code;
49 adev->virt.vf_errors.flags [index] = error_flags;
50 adev->virt.vf_errors.data [index] = error_data;
51 adev->virt.vf_errors.write_count ++;
52 mutex_unlock(&adev->virt.vf_errors.lock);
56 void amdgpu_vf_error_trans_all(struct amdgpu_device *adev) argument
[all...]
H A Damdgpu_nbio.h54 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
55 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
56 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
57 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
58 u32 (*get_rev_id)(struct amdgpu_device *adev);
59 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
60 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
61 u32 (*get_memsize)(struct amdgpu_device *adev);
62 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
64 void (*vcn_doorbell_range)(struct amdgpu_device *adev, boo
[all...]
H A Damdgpu_vega10_reg_init.c34 int vega10_reg_base_init(struct amdgpu_device *adev) argument
39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
40 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
41 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
42 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
43 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
44 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
45 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
46 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
47 adev
63 vega10_doorbell_index_init(struct amdgpu_device * adev) argument
[all...]
H A Damdgpu_xgmi.h39 struct amdgpu_device *adev; member in struct:amdgpu_hive_info
44 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev, int lock);
45 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);
46 int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
47 void amdgpu_xgmi_remove_device(struct amdgpu_device *adev);
48 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate);
49 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
51 int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev);
52 void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev);
54 static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev, argument
[all...]
H A Dmmhub_v1_0.h30 u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev);
31 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev);
32 void mmhub_v1_0_gart_disable(struct amdgpu_device *adev);
33 void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
35 void mmhub_v1_0_init(struct amdgpu_device *adev);
36 int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
38 void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags);
39 void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
41 void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
H A Damdgpu_umc.h27 void (*err_cnt_init)(struct amdgpu_device *adev);
28 int (*ras_late_init)(struct amdgpu_device *adev);
29 void (*query_ras_error_count)(struct amdgpu_device *adev,
31 void (*query_ras_error_address)(struct amdgpu_device *adev,
33 void (*init_registers)(struct amdgpu_device *adev);
52 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev);
53 void amdgpu_umc_ras_fini(struct amdgpu_device *adev);
54 int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
57 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
H A Dnv.h31 void nv_grbm_select(struct amdgpu_device *adev,
33 int nv_set_ip_blocks(struct amdgpu_device *adev);
34 int navi10_reg_base_init(struct amdgpu_device *adev);
35 int navi14_reg_base_init(struct amdgpu_device *adev);
36 int navi12_reg_base_init(struct amdgpu_device *adev);
H A Damdgpu_discovery.h31 int amdgpu_discovery_init(struct amdgpu_device *adev);
32 void amdgpu_discovery_fini(struct amdgpu_device *adev);
33 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
34 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
36 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);
H A Damdgpu_mmhub.c32 int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev) argument
43 if (!adev->mmhub.ras_if) {
44 adev->mmhub.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
45 if (!adev->mmhub.ras_if)
47 adev->mmhub.ras_if->block = AMDGPU_RAS_BLOCK__MMHUB;
48 adev->mmhub.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
49 adev->mmhub.ras_if->sub_block_index = 0;
50 strcpy(adev->mmhub.ras_if->name, "mmhub");
52 ih_info.head = fs_info.head = *adev->mmhub.ras_if;
53 r = amdgpu_ras_late_init(adev, ade
63 amdgpu_mmhub_ras_fini(struct amdgpu_device * adev) argument
[all...]
H A Damdgpu_mmhub.h27 void (*ras_init)(struct amdgpu_device *adev);
28 int (*ras_late_init)(struct amdgpu_device *adev);
29 void (*query_ras_error_count)(struct amdgpu_device *adev,
38 int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev);
39 void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev);
H A Damdgpu_nbio.c30 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev) argument
41 if (!adev->nbio.ras_if) {
42 adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
43 if (!adev->nbio.ras_if)
45 adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;
46 adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
47 adev->nbio.ras_if->sub_block_index = 0;
48 strcpy(adev->nbio.ras_if->name, "pcie_bif");
50 ih_info.head = fs_info.head = *adev->nbio.ras_if;
51 r = amdgpu_ras_late_init(adev, ade
77 amdgpu_nbio_ras_fini(struct amdgpu_device * adev) argument
[all...]
H A Damdgpu_soc15.c102 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) argument
106 address = adev->nbio.funcs->get_pcie_index_offset(adev);
107 data = adev->nbio.funcs->get_pcie_data_offset(adev);
109 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
113 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
117 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) argument
121 address = adev->nbio.funcs->get_pcie_index_offset(adev);
132 soc15_pcie_rreg64(struct amdgpu_device * adev,u32 reg) argument
153 soc15_pcie_wreg64(struct amdgpu_device * adev,u32 reg,u64 v) argument
175 soc15_uvd_ctx_rreg(struct amdgpu_device * adev,u32 reg) argument
190 soc15_uvd_ctx_wreg(struct amdgpu_device * adev,u32 reg,u32 v) argument
203 soc15_didt_rreg(struct amdgpu_device * adev,u32 reg) argument
218 soc15_didt_wreg(struct amdgpu_device * adev,u32 reg,u32 v) argument
231 soc15_gc_cac_rreg(struct amdgpu_device * adev,u32 reg) argument
243 soc15_gc_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v) argument
253 soc15_se_cac_rreg(struct amdgpu_device * adev,u32 reg) argument
265 soc15_se_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v) argument
275 soc15_get_config_memsize(struct amdgpu_device * adev) argument
280 soc15_get_xclk(struct amdgpu_device * adev) argument
291 soc15_grbm_select(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue,u32 vmid) argument
303 soc15_vga_set_state(struct amdgpu_device * adev,bool state) argument
308 soc15_read_disabled_bios(struct amdgpu_device * adev) argument
314 soc15_read_bios_from_rom(struct amdgpu_device * adev,u8 * bios,u32 length_bytes) argument
363 soc15_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset) argument
380 soc15_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset) argument
395 soc15_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value) argument
428 soc15_program_register_sequence(struct amdgpu_device * adev,const struct soc15_reg_golden * regs,const u32 array_size) argument
460 soc15_asic_mode1_reset(struct amdgpu_device * adev) argument
494 soc15_asic_baco_reset(struct amdgpu_device * adev) argument
515 soc15_asic_reset_method(struct amdgpu_device * adev) argument
550 soc15_asic_reset(struct amdgpu_device * adev) argument
570 soc15_supports_baco(struct amdgpu_device * adev) argument
592 soc15_set_uvd_clocks(struct amdgpu_device * adev,u32 vclk,u32 dclk) argument
605 soc15_set_vce_clocks(struct amdgpu_device * adev,u32 evclk,u32 ecclk) argument
612 soc15_pcie_gen3_enable(struct amdgpu_device * adev) argument
630 soc15_program_aspm(struct amdgpu_device * adev) argument
639 soc15_enable_doorbell_aperture(struct amdgpu_device * adev,bool enable) argument
655 soc15_get_rev_id(struct amdgpu_device * adev) argument
660 soc15_set_ip_blocks(struct amdgpu_device * adev) argument
821 soc15_flush_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring) argument
826 soc15_invalidate_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring) argument
836 soc15_need_full_reset(struct amdgpu_device * adev) argument
841 soc15_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1) argument
888 vega20_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1) argument
937 soc15_need_reset_on_init(struct amdgpu_device * adev) argument
960 soc15_get_pcie_replay_count(struct amdgpu_device * adev) argument
1019 struct amdgpu_device *adev = (struct amdgpu_device *)handle; local in function:soc15_common_early_init
1247 struct amdgpu_device *adev = (struct amdgpu_device *)handle; local in function:soc15_common_late_init
1261 struct amdgpu_device *adev = (struct amdgpu_device *)handle; local in function:soc15_common_sw_init
1273 struct amdgpu_device *adev = (struct amdgpu_device *)handle; local in function:soc15_common_sw_fini
1280 soc15_doorbell_range_init(struct amdgpu_device * adev) argument
1301 struct amdgpu_device *adev = (struct amdgpu_device *)handle; local in function:soc15_common_hw_init
1330 struct amdgpu_device *adev = (struct amdgpu_device *)handle; local in function:soc15_common_hw_fini
1350 struct amdgpu_device *adev = (struct amdgpu_device *)handle; local in function:soc15_common_suspend
1357 struct amdgpu_device *adev = (struct amdgpu_device *)handle; local in function:soc15_common_resume
1377 soc15_update_hdp_light_sleep(struct amdgpu_device * adev,bool enable) argument
1411 soc15_update_drm_clock_gating(struct amdgpu_device * adev,bool enable) argument
1440 soc15_update_drm_light_sleep(struct amdgpu_device * adev,bool enable) argument
1455 soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable) argument
1476 struct amdgpu_device *adev = (struct amdgpu_device *)handle; local in function:soc15_common_set_clockgating_state
1527 struct amdgpu_device *adev = (struct amdgpu_device *)handle; local in function:soc15_common_get_clockgating_state
[all...]
H A Dcik.h31 void cik_srbm_select(struct amdgpu_device *adev,
33 int cik_set_ip_blocks(struct amdgpu_device *adev);
35 void legacy_doorbell_index_init(struct amdgpu_device *adev);
H A Dgfx_v9_0.h31 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num);
33 uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
34 int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info);
/src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_irq.h44 int amdgpu_dm_irq_init(struct amdgpu_device *adev);
52 void amdgpu_dm_irq_fini(struct amdgpu_device *adev);
57 * @adev: AMD DRM device
68 void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
77 * @adev: AMD DRM device.
81 void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
85 void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev);
87 void amdgpu_dm_hpd_init(struct amdgpu_device *adev);
88 void amdgpu_dm_hpd_fini(struct amdgpu_device *adev);
94 int amdgpu_dm_irq_suspend(struct amdgpu_device *adev);
[all...]

Completed in 35 milliseconds

1234567891011>>