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    Searched refs:asic_id (Results 1 - 25 of 28) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/
amdgpu_clk_mgr.c 99 struct hw_asic_id asic_id = ctx->asic_id; local in function:dc_clk_mgr_create
108 switch (asic_id.chip_family) {
117 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
118 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
122 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
123 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
124 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
128 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) {
134 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
dce110_resource.h 48 struct hw_asic_id asic_id);
amdgpu_dce110_resource.c 562 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ?
1314 struct hw_asic_id *asic_id)
1316 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))
1326 struct hw_asic_id asic_id)
1334 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);
1494 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1508 struct hw_asic_id asic_id)
1516 if (dce110_resource_construct(num_virtual_links, dc, pool, asic_id))
amdgpu_dce110_compressor.c 522 compressor->base.memory_bus_width = ctx->asic_id.vram_width;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
resource.h 40 struct hw_asic_id asic_id);
dce_calcs.h 474 struct hw_asic_id asic_id);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/
amdgpu_dce112_clk_mgr.c 109 if (!ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))
185 if (!ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_resource.c 63 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
66 switch (asic_id.chip_family) {
72 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
73 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
74 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
84 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
85 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
89 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
90 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
91 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
    [all...]
amdgpu_dc_stream.c 247 if (stream->ctx->asic_id.chip_family == FAMILY_RV &&
248 ASICREV_IS_RAVEN(stream->ctx->asic_id.hw_internal_rev)) {
amdgpu_dc.c 602 dc_ctx->asic_id = init_params->asic_id;
609 dc_version = resource_parse_asic_id(init_params->asic_id);
696 bp_init_data.bios = init_params->asic_id.atombios_base_address;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/
amdgpu_dce110_clk_mgr.c 203 if (ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
amdgpu_dce112_resource.c 1184 struct hw_asic_id *asic_id)
1186 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
1187 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev))
1203 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
1372 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
amdgpu_dce112_compressor.c 818 compressor->base.memory_bus_width = ctx->asic_id.vram_width;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 1231 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3223 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
3329 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3331 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3336 if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
3341 if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
3493 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
3495 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
3497 get_dml_project_version(ctx->asic_id.hw_internal_rev);
3504 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev))
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_resource.c 1442 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1449 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
1459 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_types.h 107 struct hw_asic_id asic_id; member in struct:dc_context
dc.h 553 struct hw_asic_id asic_id; member in struct:dc_init_data
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu71_discrete.h 562 uint32_t asic_id; member in struct:SMU71_Discrete_Log_Header_Table
smu72_discrete.h 629 uint32_t asic_id; member in struct:SMU7_Discrete_Log_Header_Table
smu73_discrete.h 664 uint32_t asic_id; member in struct:SMU7_Discrete_Log_Header_Table
smu74_discrete.h 629 uint32_t asic_id; member in struct:SMU7_Discrete_Log_Header_Table
smu75_discrete.h 658 uint32_t asic_id; member in struct:SMU7_Discrete_Log_Header_Table
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dce_calcs.c 54 static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asic_id)
56 switch (asic_id.chip_family) {
59 if (ASIC_REV_IS_STONEY(asic_id.hw_internal_rev))
64 if (ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
66 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev))
68 if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev))
70 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
2036 struct hw_asic_id asic_id)
2041 enum bw_calcs_version version = bw_calcs_version_from_asic_id(asic_id);
2049 vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_resource.c 1042 bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
1234 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_clk_mgr.c 325 if (!ASICREV_IS_VEGA20_P(clk_mgr->ctx->asic_id.hw_internal_rev))

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