| /src/sys/dev/pci/ |
| pciide_apollo_reg.h | 98 #define APO_IDECONF_EN(channel) (0x00000001 << (1 - (channel)))
105 #define APO_IDECONF_WR_BUFF_EN(channel) (0x00001000 << ((1 - (channel)) << 1))
106 #define APO_IDECONF_RD_PREF_EN(channel) (0x00002000 << ((1 - (channel)) << 1))
109 #define APO_IDECONF_IO_NAT(channel) \
110 (0x00400000 << (1 - (channel))) /* VIA 580 only */
111 #define APO_IDECONF_FIFO_TRSH(channel, x) \
112 ((x) & 0x3) << ((1 - (channel)) << 1 + 24
[all...] |
| pciide_acard_reg.h | 27 #define ATP850_IDETIME(channel) (0x40 + (channel) * 4)
32 #define ATP860_SETTIME(channel, drive, act, rec) \
34 ((channel) * 16 + (drive) * 8))
35 #define ATP860_SETTIME_MASK(channel) (0xffff << ((channel) * 16))
47 #define ATP850_UDMA_MODE(channel, drive, x) \
48 (((x) & 0x3) << ((channel) * 4 + (drive) * 2))
49 #define ATP860_UDMA_MODE(channel, drive, x) \
50 (((x) & 0xf) << ((channel) * 8 + (drive) * 4)
[all...] |
| pciide_piix_reg.h | 47 * 0x40/0x41 is for primary, 0x42/0x43 for secondary channel
50 #define PIIX_IDETIM_READ(x, channel) (((x) >> (16 * (channel))) & 0x0000FFFF)
51 #define PIIX_IDETIM_SET(x, bytes, channel) \
52 ((x) | ((unsigned int)(bytes) << (16 * (channel))))
53 #define PIIX_IDETIM_CLEAR(x, bytes, channel) \
54 ((x) & ~((unsigned int)(bytes) << (16 * (channel))))
74 #define PIIX_SIDETIM_ISP_MASK(channel) (0x0c << ((channel) * 4))
76 #define PIIX_SIDETIM_ISP_SET(x, channel) \
[all...] |
| pciide_pdc202xx_reg.h | 41 #define PDC246_STATE_LBA(channel) (0x0100 << (channel))
43 #define PDC246_STATE_EN(channel) (0x0002 << (channel))
49 #define PDC2xx_TIM(channel, drive) (0x60 + 4 * (drive) + 8 * (channel))
75 #define PDC2xx_SCR_EMPTY(channel) (0x00000100 << (4 * channel))
76 #define PDC2xx_SCR_FULL(channel) (0x00000200 << (4 * channel))
[all...] |
| pciide_sis_reg.h | 34 #define SIS_TIM(channel) (0x40 + (channel * 4))
49 #define SIS_TIM133(reg57, channel, drive) \
50 ((((reg57) & 0x40) ? 0x70 : 0x40) + ((channel) << 3) + ((drive) << 2))
80 #define SIS_REG_CBL_33(channel) (0x10 << (channel))
81 #define SIS96x_REG_CBL(channel) (0x51 + (channel) * 2)
|
| stpcide.c | 91 int channel; local in function:stpc_chip_map
116 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
117 channel++) {
118 cp = &sc->pciide_channels[channel];
119 if (pciide_chansetup(sc, channel, interface) == 0)
147 int channel = chp->ch_channel; local in function:stpc_setup_channel
185 (channel == 0) ? 0x40 : 0x44);
187 channel, idetim, (bits[1] << 16) | bits[0]);
191 (channel == 0) ? 0x40 : 0x44, idetim)
[all...] |
| iteide.c | 100 int channel; local in function:ite_chip_map
146 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; channel++) {
147 cp = &sc->pciide_channels[channel];
149 if (pciide_chansetup(sc, channel, interface) == 0)
170 int channel = chp->ch_channel; local in function:ite_setup_channel
176 tim = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_TIM(channel));
179 channel, tim), DEBUG_PROBE);
184 /* Clear all bits for this channel */
[all...] |
| /src/sys/arch/sun2/include/ |
| z8530var.h | 94 * On a Sun2, the keyboard is always on zs1 channel 0,
95 * and the mouse is always on zs1 channel 1.
97 #define zs_peripheral_type(promunit, node, channel) ((promunit) == 1 ? ((channel) == 0 ? ZS_PERIPHERAL_SUNKBD : ZS_PERIPHERAL_SUNMS) : ZS_PERIPHERAL_UNKNOWN)
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| sun8i-v3s-licheepi-zero-dock.dts | 74 channel = <0>;
81 channel = <0>;
88 channel = <0>;
95 channel = <0>;
|
| imx6q-display5-tianma-tm070-1280x768.dts | 47 lvds0: lvds-channel@0 {
|
| sun6i-a31s-inet-q972.dts | 77 channel = <0>;
84 channel = <0>;
91 channel = <0>;
|
| sun8i-a23-evb.dts | 82 channel = <0>;
89 channel = <0>;
96 channel = <0>;
|
| aspeed-bmc-ampere-mtjade.dts | 146 compatible = "io-channel-mux";
148 #io-channel-cells = <1>;
149 io-channel-names = "parent";
155 compatible = "io-channel-mux";
157 #io-channel-cells = <1>;
158 io-channel-names = "parent";
164 compatible = "io-channel-mux";
166 #io-channel-cells = <1>;
167 io-channel-names = "parent";
173 compatible = "io-channel-mux"
[all...] |
| sunxi-reference-design-tablet.dtsi | 66 channel = <0>;
73 channel = <0>;
|
| /src/sys/arch/luna68k/dev/ |
| sio.c | 77 int channel; local in function:sio_attach
84 for (channel = 0; channel < 2; channel++) {
85 sc->sc_intrhand[channel].ih_func = nullintr;
86 sio_args.channel = channel;
87 sio_args.hwflags = (channel == sysconsole);
102 if (args->channel != -1)
103 aprint_normal(" channel %d", args->channel)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/vmwgfx/ |
| vmwgfx_msg.c | 90 * @channel: RPC channel
95 static int vmw_open_channel(struct rpc_channel *channel, unsigned int protocol)
108 channel->channel_id = HIGH_WORD(edx);
109 channel->cookie_high = si;
110 channel->cookie_low = di;
120 * @channel: RPC channel
124 static int vmw_close_channel(struct rpc_channel *channel)
129 si = channel->cookie_high
426 struct rpc_channel channel; local in function:vmw_host_get_guestinfo
491 struct rpc_channel channel; local in function:vmw_host_log
546 struct rpc_channel channel; local in function:vmw_msg_ioctl
[all...] |
| /src/sys/arch/x68k/dev/ |
| opm.c | 166 opm_key_on(u_char channel)
168 writeopm(0x08, opm0->sc_vdata[channel].sm << 3 | channel);
172 opm_key_off(u_char channel)
174 writeopm(0x08, channel);
178 opm_set_voice(int channel, struct opm_voice *voice)
180 memcpy(&opm0->sc_vdata[channel], voice, sizeof(struct opm_voice));
182 opm_set_voice_sub(0x40 + channel, &voice->m1);
183 opm_set_voice_sub(0x48 + channel, &voice->m2);
184 opm_set_voice_sub(0x50 + channel, &voice->c1)
[all...] |
| /src/sys/arch/acorn32/eb7500atx/ |
| rside.c | 82 * secondary channel.
132 * index = channel
164 int channel, i; local in function:rside_attach
186 /* Fill in wdc and channel infos */
192 for (channel = 0 ; channel < 2; channel++) {
193 scp = &sc->rside_channels[channel];
194 sc->sc_chanarray[channel] = &scp->rc_channel;
196 wdr = &sc->sc_wdc_regs[channel];
[all...] |
| /src/sys/arch/arm/imx/ |
| imx23_apbdma.c | 261 * Initialize DMA channel.
264 apbdma_chan_init(struct apbdma_softc *sc, unsigned int channel)
270 DMA_WR(sc, HW_APB_CTRL1_SET, (1<<channel)<<16);
278 * Set command chain for DMA channel.
280 #define HW_APB_CHN_NXTCMDAR(base, channel) (base + (0x70 * channel))
282 apbdma_chan_set_chain(struct apbdma_softc *sc, unsigned int channel,
288 reg = HW_APB_CHN_NXTCMDAR(HW_APBH_CH0_NXTCMDAR, channel);
290 reg = HW_APB_CHN_NXTCMDAR(HW_APBX_CH0_NXTCMDAR, channel);
302 #define HW_APB_CHN_SEMA(base, channel) (base + (0x70 * channel)
[all...] |
| /src/sys/arch/ews4800mips/sbd/ |
| zs_sbdio.c | 116 int s, channel; local in function:zs_sbdio_attach
125 * Initialize software state for each channel.
127 for (channel = 0; channel < 2; channel++) {
128 zsc_args.channel = channel;
130 cs = &zsc->zsc_cs_store[channel];
131 zsc->zsc_cs[channel] = cs;
133 cs->cs_channel = channel;
[all...] |
| /src/sys/arch/macppc/dev/ |
| dbdma.h | 96 #define DBDMA_REGMAP(channel) \
98 + (channel << 8))
136 * DBDMA Channel layout
162 void dbdma_start(dbdma_regmap_t *channel, dbdma_command_t *commands);
163 void dbdma_stop(dbdma_regmap_t *channel);
164 void dbdma_flush(dbdma_regmap_t *channel);
165 void dbdma_reset(dbdma_regmap_t *channel);
166 void dbdma_continue(dbdma_regmap_t *channel);
167 void dbdma_pause(dbdma_regmap_t *channel);
|
| /src/sys/dev/bluetooth/ |
| btsco.h | 42 #define BTSCOchannel "rfcomm-channel"
46 * from the audio device so that the control channel can be set up
52 uint8_t channel; /* RFCOMM channel */ member in struct:btsco_info
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/ |
| nouveau_abi16.h | 51 int channel; member in struct:drm_nouveau_channel_alloc
66 int channel; member in struct:drm_nouveau_channel_free
70 int channel; member in struct:drm_nouveau_grobj_alloc
76 uint32_t channel; member in struct:drm_nouveau_notifierobj_alloc
83 int channel; member in struct:drm_nouveau_gpuobj_free
|
| /src/sys/arch/newsmips/dev/ |
| zs_hb.c | 132 zs_get_chan_addr(int zs_unit, int channel)
142 if (channel == 0) {
200 int s, zs_unit, channel, intlevel; local in function:zs_hb_attach
222 * Initialize software state for each channel.
224 for (channel = 0; channel < 2; channel++) {
225 zsc_args.channel = channel;
226 zsc_args.hwflags = zs_hwflags[zs_unit][channel];
[all...] |
| /src/sys/arch/mac68k/mac68k/ |
| psc.c | 337 start_psc_dma(int channel, int *rset, bus_addr_t addr, uint32_t len, int datain)
343 chan_ctrl = PSC_CTLBASE + (channel << 4);
345 pause_psc_dma(channel);
349 rset_addr = PSC_ADDRBASE + (0x20 * channel) + *rset;
372 pause_psc_dma(int channel)
378 chan_ctrl = PSC_CTLBASE + (channel << 4);
391 wait_psc_dma(int channel, int rset, uint32_t *residual)
397 rset_addr = PSC_ADDRBASE + (0x20 * channel) + rset;
418 stop_psc_dma(int channel, int rset, uint32_t *residual, int datain)
425 rval = stop_read_psc_dma(channel, rset, residual)
[all...] |
