| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_afmt.c | 39 /* Clock N CTS N CTS N CTS */
54 * calculate CTS and N values if they are not found in the table
56 static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq)
58 int n, cts; local in function:amdgpu_afmt_calc_cts
63 cts = clock * 1000;
66 div = gcd(n, cts);
69 cts /= div;
78 cts *= mul
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| imx6qdl-dhcom-drc02.dtsi | 15 * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD
16 * card must be disabled and the uart1 rts/cts must be output on other DHCOM
73 * DHCOM UART1 rts/cts pins. Therefore this UART have to use DHCOM GPIOs
74 * for rts/cts. So configure DHCOM GPIO I as rts and GPIO M as cts.
77 cts-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; /* GPIO M */
86 * controlled by DHCOM GPIO P. So remove rts/cts pins and the property
117 * M: uart1 cts
|
| stm32mp157a-iot-box.dts | 57 /* Note: HW flow control is broken, hence using custom CTS/RTS gpios */
59 cts-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
|
| sun5i-gr8.dtsi | 122 uart1_cts_rts_pins: uart1-cts-rts-pins {
|
| rk3066a.dtsi | 513 uart0_cts: uart0-cts {
528 uart1_cts: uart1-cts {
542 /* no rts / cts for uart2 */
551 uart3_cts: uart3-cts {
|
| rk3188.dtsi | 475 uart0_cts: uart0-cts {
490 uart1_cts: uart1-cts {
504 /* no rts / cts for uart2 */
513 uart3_cts: uart3-cts {
|
| sun7i-a20.dtsi | 1082 uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins {
1094 uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins {
1106 uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
1118 uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
1130 uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins {
|
| bcm2711.dtsi | 942 pin-cts {
966 pin-cts {
990 pin-cts {
1014 pin-cts {
|
| r8a7742-iwg21d-q7-dbcm-ca.dts | 195 cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
|
| sun5i.dtsi | 577 uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins {
587 uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
|
| sunxi-h3-h5.dtsi | 489 uart1_rts_cts_pins: uart1-rts-cts-pins {
499 uart2_rts_cts_pins: uart2-rts-cts-pins {
509 uart3_rts_cts_pins: uart3-rts-cts-pins {
|
| rk3036.dtsi | 822 uart0_cts: uart0-cts {
836 /* no rts / cts for uart1 */
844 /* no rts / cts for uart2 */
|
| /src/sys/arch/atari/stand/ahdilabel/ |
| ahdilabel.c | 299 sec_to_cts (struct ahdi_ptable *ptable, u_int32_t sector, char *cts, size_t len)
307 snprintf (cts, len, "%u/%u/%u", cylinder, track, sector);
308 return (cts);
370 char buf[BUFLEN], cts[CTSLEN]; local in function:change_part
391 sec_to_cts (ptable, ptable->parts[part].root, cts, sizeof(cts)));
398 sec_to_cts (ptable, ptable->parts[part].start, cts, sizeof(cts)));
405 sec_to_cts (ptable, ptable->parts[part].size, cts, sizeof(cts)),
[all...] |
| /src/sys/dev/ic/ |
| athrate-sample.h | 191 int rts, cts; local in function:calc_usecs_unicast_packet
237 rts = cts = 0;
244 cts = 1;
254 if (rts || cts) {
267 if (rts) /* SIFS + CTS */
273 if (cts) /* SIFS + ACK */
|
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/ralink/ |
| gardena_smart_gateway_mt7688.dts | 184 cts-gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
195 cts-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_audio.c | 552 * calculate CTS and N values if they are not found in the table
554 static void radeon_audio_calc_cts(unsigned int clock, int *CTS, int *N, int freq)
556 int n, cts; local in function:radeon_audio_calc_cts
561 cts = clock * 1000;
564 div = gcd(n, cts);
567 cts /= div;
576 cts *= mul;
585 *CTS = cts;
587 DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n"
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/canaan/ |
| k210.dtsi | 211 cts-override;
228 cts-override;
245 cts-override;
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/ |
| imx8mm-venice-gw7901.dts | 639 cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
656 cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
664 cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
|
| imx8mm-venice-gw7902.dts | 565 cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
581 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
595 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
798 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */
827 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
836 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */
|
| imx8mm-venice-gw73xx.dtsi | 150 cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
|
| /src/sys/net80211/ |
| ieee80211_output.c | 743 /* RTS reserves medium for SIFS | CTS | SIFS | (DATA) | SIFS | ACK
770 /* 1 - 2 Mb/s WLAN: send ACK/CTS at 1 Mb/s */
776 /* 5.5 - 11 Mb/s WLAN: send ACK/CTS at 2 Mb/s */
1802 * Build a CTS-to-self (Clear To Send) control frame.
1807 struct ieee80211_frame_cts *cts; local in function:ieee80211_get_cts_to_self
1816 cts = mtod(m, struct ieee80211_frame_cts *);
1817 cts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL |
1819 cts->i_fc[1] = IEEE80211_FC1_DIR_NODS;
1820 *(uint16_t *)cts->i_dur = htole16(dur);
1821 IEEE80211_ADDR_COPY(cts->i_ra, ic->ic_myaddr)
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/ |
| qcs404-evb.dtsi | 380 cts {
|
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/img/ |
| pistachio.dtsi | 557 uart0_rts_cts_pins: uart0-rts-cts-pins {
558 uart0-rts-cts {
573 uart1_rts_cts_pins: uart1-rts-cts-pins {
574 uart1-rts-cts {
|
| /src/sys/arch/arm/sunxi/ |
| sunxi_hdmi.c | 1000 uint32_t cts, n, val; local in function:sunxi_hdmi_set_audiomode
1048 cts = ((mode->dot_clock * 10) * (n / 128)) / 480;
1049 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTS_REG, cts);
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/ |
| rk3368.dtsi | 1156 uart0_cts: uart0-cts {
1171 uart1_cts: uart1-cts {
1185 /* no rts / cts for uart2 */
1194 uart3_cts: uart3-cts {
1209 uart4_cts: uart4-cts {
|
