| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dpm.c | 114 if (rps == adev->pm.dpm.current_ps)
116 if (rps == adev->pm.dpm.requested_ps)
118 if (rps == adev->pm.dpm.boot_ps)
129 adev->pm.dpm.new_active_crtcs = 0;
130 adev->pm.dpm.new_active_crtc_count = 0;
136 adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
137 adev->pm.dpm.new_active_crtc_count++;
269 adev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
270 adev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
271 adev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime)
[all...] |
| amdgpu_kv_dpm.c | 81 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
103 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
384 struct kv_power_info *pi = adev->pm.dpm.priv;
808 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
910 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
983 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1044 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1110 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1169 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1236 adev->pm.dpm.current_ps = &pi->current_rps
[all...] |
| amdgpu_si_dpm.c | 1864 struct si_power_info *pi = adev->pm.dpm.priv;
1937 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1938 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1966 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1973 struct ni_power_info *pi = adev->pm.dpm.priv;
2227 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2230 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2233 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2234 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit)
[all...] |
| amdgpu_pm.c | 182 pm = adev->pm.dpm.user_state;
186 pm = adev->pm.dpm.user_state;
225 adev->pm.dpm.user_state = state;
231 adev->pm.dpm.user_state = state;
323 level = adev->pm.dpm.forced_level;
412 if (adev->pm.dpm.thermal_active) {
425 adev->pm.dpm.forced_level = level;
978 * NOTE: change to the dcefclk max dpm level is not supported now
1467 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps
[all...] |
| amdgpu_dpm.h | 438 /* dpm */
441 struct amdgpu_dpm dpm; member in struct:amdgpu_pm
|
| amdgpu_drv.c | 271 * DOC: dpm (int)
276 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
277 module_param_named(dpm, amdgpu_dpm, int, 0444);
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_r600_dpm.c | 152 if (rps == rdev->pm.dpm.current_ps)
154 if (rps == rdev->pm.dpm.requested_ps)
156 if (rps == rdev->pm.dpm.boot_ps)
763 rdev->pm.dpm.thermal.min_temp = low_temp;
764 rdev->pm.dpm.thermal.max_temp = high_temp;
863 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
864 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
865 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
900 rdev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst;
901 rdev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin)
[all...] |
| radeon_pm.c | 84 rdev->pm.dpm.ac_power = true;
86 rdev->pm.dpm.ac_power = false;
88 if (rdev->asic->dpm.enable_bapm)
89 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
438 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
456 /* we don't support the legacy modes with dpm */
491 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
508 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
510 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
512 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE
[all...] |
| radeon_ci_dpm.c | 202 struct ci_power_info *pi = rdev->pm.dpm.priv;
287 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
289 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
291 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
292 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
295 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
296 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
297 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
298 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
299 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3)
[all...] |
| radeon_rs780_dpm.c | 49 struct igp_power_info *pi = rdev->pm.dpm.priv;
386 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
413 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
606 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
658 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
659 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
748 rdev->pm.dpm.boot_ps = rps;
750 rdev->pm.dpm.uvd_ps = rps;
813 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,
816 if (!rdev->pm.dpm.ps
[all...] |
| radeon_btc_dpm.c | 1236 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values,
1243 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values,
1286 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio)
1290 (rdev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
1291 rdev->pm.dpm.dyn_state.mclk_sclk_ratio);
1293 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta)
1297 rdev->pm.dpm.dyn_state.sclk_mclk_delta);
1324 if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) {
1326 (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta));
1330 if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta)
[all...] |
| radeon_rv770_dpm.c | 61 struct rv7xx_power_info *pi = rdev->pm.dpm.priv;
68 struct evergreen_power_info *pi = rdev->pm.dpm.priv;
200 DRM_DEBUG("Could not force DPM to low.\n");
1195 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) {
1198 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT)
1201 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT)
1205 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1351 if (rdev->pm.dpm.new_active_crtcs & 1) {
1354 } else if (rdev->pm.dpm.new_active_crtcs & 2) {
1503 rdev->pm.dpm.forced_level = level
[all...] |
| radeon_rv6xx_dpm.c | 50 struct rv6xx_power_info *pi = rdev->pm.dpm.priv;
926 rdev->pm.dpm.voltage_response_time,
930 rdev->pm.dpm.backbias_response_time,
1190 if (rdev->pm.dpm.new_active_crtcs & 1) {
1193 } else if (rdev->pm.dpm.new_active_crtcs & 2) {
1303 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);
1553 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1558 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1620 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1638 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS
[all...] |
| radeon_si_dpm.c | 1771 struct si_power_info *pi = rdev->pm.dpm.priv;
1845 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1846 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
2136 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2139 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2142 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2143 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2145 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2146 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit
[all...] |
| radeon_ni_dpm.c | 734 struct ni_power_info *pi = rdev->pm.dpm.priv;
801 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
807 if (rdev->pm.dpm.ac_power)
808 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
810 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
812 if (rdev->pm.dpm.ac_power == false) {
879 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
882 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
885 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
888 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk
[all...] |
| radeon_kv_dpm.c | 257 struct kv_power_info *pi = rdev->pm.dpm.priv;
562 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
584 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
725 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
827 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
900 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
961 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1027 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1086 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1286 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps)
[all...] |
| radeon_trinity_dpm.c | 362 struct trinity_power_info *pi = rdev->pm.dpm.priv;
1066 rdev->pm.dpm.thermal.min_temp = low_temp;
1067 rdev->pm.dpm.thermal.max_temp = high_temp;
1129 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1177 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1232 rdev->pm.dpm.forced_level = level;
1240 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1261 trinity_dpm_bapm_enable(rdev, rdev->pm.dpm.ac_power);
1515 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1552 u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count
[all...] |
| radeon_cypress_dpm.c | 1641 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1644 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1647 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1754 if (rdev->pm.dpm.new_active_crtc_count > 0)
1759 if (rdev->pm.dpm.new_active_crtc_count > 1)
1769 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
1770 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
1773 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
1786 cypress_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
1813 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps
[all...] |
| radeon_sumo_dpm.c | 88 struct sumo_power_info *pi = rdev->pm.dpm.priv;
1179 rdev->pm.dpm.thermal.min_temp = low_temp;
1180 rdev->pm.dpm.thermal.max_temp = high_temp;
1237 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1282 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1288 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1427 rdev->pm.dpm.boot_ps = rps;
1431 rdev->pm.dpm.uvd_ps = rps;
1489 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
1492 if (!rdev->pm.dpm.ps
[all...] |
| radeon_uvd.c | 884 radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd,
885 &rdev->pm.dpm.hd);
906 if ((rdev->pm.dpm.sd != sd) ||
907 (rdev->pm.dpm.hd != hd)) {
908 rdev->pm.dpm.sd = sd;
909 rdev->pm.dpm.hd = hd;
|
| radeon.h | 1245 /* not used for dpm */
1693 /* dpm */
1696 struct radeon_dpm dpm; member in struct:radeon_pm
2037 } dpm; member in struct:radeon_asic
2849 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2850 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2851 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2852 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2853 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2854 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)
[all...] |
| radeon_asic.c | 1090 .dpm = {
1185 .dpm = {
1293 .dpm = {
1415 .dpm = {
1511 .dpm = {
1606 .dpm = {
1756 .dpm = {
1879 .dpm = {
2019 .dpm = {
2191 .dpm =
[all...] |
| radeon_drv.c | 276 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
277 module_param_named(dpm, radeon_dpm, int, 0444);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_hardwaremanager.c | 91 pr_info("dpm has been enabled\n");
111 pr_info("dpm has been disabled\n");
263 adev->pm.dpm.thermal.min_temp = range.min;
264 adev->pm.dpm.thermal.max_temp = range.max;
265 adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
266 adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
267 adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
268 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
269 adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
270 adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_smu_v11_0.c | 1231 adev->pm.dpm.thermal.min_temp = range.min;
1232 adev->pm.dpm.thermal.max_temp = range.max;
1233 adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1234 adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1235 adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1236 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1237 adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1238 adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1239 adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1848 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM
[all...] |
