| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| rv770_dpm.h | 183 u32 engine_clock,
186 u32 engine_clock, u32 memory_clock,
204 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
207 u32 engine_clock, u32 memory_clock,
229 u32 engine_clock);
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| radeon_rv740_dpm.c | 125 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
142 engine_clock, false, ÷rs);
148 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
165 u32 vco_freq = engine_clock * dividers.post_div;
181 sclk->sclk_value = cpu_to_be32(engine_clock);
192 u32 engine_clock, u32 memory_clock,
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| radeon_rv730_dpm.c | 45 u32 engine_clock,
62 engine_clock, false, ÷rs);
74 tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
97 u32 vco_freq = engine_clock * post_divider;
113 sclk->sclk_value = cpu_to_be32(engine_clock);
124 u32 engine_clock, u32 memory_clock,
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| cypress_dpm.h | 127 u32 engine_clock, u32 memory_clock);
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| radeon_rv770_dpm.c | 391 u32 engine_clock, u32 memory_clock,
489 u32 engine_clock,
511 engine_clock, false, ÷rs);
522 tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
544 u32 vco_freq = engine_clock * post_divider;
560 sclk->sclk_value = cpu_to_be32(engine_clock);
727 u32 engine_clock)
738 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
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| radeon_ci_dpm.c | 2502 const u32 engine_clock,
2516 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2520 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
3166 u32 engine_clock,
3182 engine_clock, false, ÷rs);
3195 u32 vco_freq = engine_clock * dividers.post_div;
3211 sclk->SclkFrequency = engine_clock;
3222 u32 engine_clock,
3229 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
3235 engine_clock, &graphic_level->MinVddc)
[all...] |
| radeon_ni_dpm.c | 2003 u32 engine_clock,
2022 engine_clock, false, ÷rs);
2029 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;
2046 u32 vco_freq = engine_clock * dividers.post_div;
2062 sclk->sclk_value = engine_clock;
2074 u32 engine_clock,
2080 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
2165 u32 engine_clock,
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| radeon_cypress_dpm.c | 480 u32 engine_clock, u32 memory_clock,
910 u32 engine_clock, u32 memory_clock)
914 u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2);
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| radeon_si_dpm.c | 1763 u32 engine_clock,
4278 u32 engine_clock)
4291 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4786 u32 engine_clock,
4805 engine_clock, false, ÷rs);
4811 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4828 u32 vco_freq = engine_clock * dividers.post_div;
4844 sclk->sclk_value = engine_clock;
4856 u32 engine_clock,
4862 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp)
[all...] |
| radeon_rv6xx_dpm.c | 787 u32 engine_clock)
796 return ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| ppatomctrl.h | 297 extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
299 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
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| amdgpu_smu7_hwmgr.c | 2926 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk)
2927 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk;
2971 sclk = smu7_ps->performance_levels[0].engine_clock;
2986 smu7_ps->performance_levels[0].engine_clock = sclk;
2989 smu7_ps->performance_levels[1].engine_clock =
2990 (smu7_ps->performance_levels[1].engine_clock >=
2991 smu7_ps->performance_levels[0].engine_clock) ?
2992 smu7_ps->performance_levels[1].engine_clock :
2993 smu7_ps->performance_levels[0].engine_clock;
3011 smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk
3333 uint32_t engine_clock, memory_clock; local in function:smu7_get_pp_table_entry_callback_func_v0
[all...] |
| smu10_hwmgr.h | 78 uint32_t engine_clock; member in struct:smu10_power_level
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| smu7_hwmgr.h | 58 uint32_t engine_clock; member in struct:smu7_performance_level
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| amdgpu_smu10_hwmgr.c | 762 smu10_ps->levels[index].engine_clock = 0;
968 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
969 clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
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| amdgpu_ppatomctrl.c | 179 uint32_t engine_clock,
188 cpu_to_le32((engine_clock & SET_CLOCK_FREQ_MASK) |
1295 const uint32_t engine_clock,
1299 ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo);
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_iceland_smumgr.c | 801 uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk)
816 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs);
847 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
868 sclk->SclkFrequency = engine_clock;
897 uint32_t engine_clock,
903 result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
907 hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock,
913 graphic_level->SclkFrequency = engine_clock;
919 engine_clock,
942 smu7_get_sleep_divider_id_from_clock(engine_clock,
[all...] |
| amdgpu_tonga_smumgr.c | 544 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
559 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs);
590 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
611 sclk->SclkFrequency = engine_clock;
622 uint32_t engine_clock,
632 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
641 vdd_dep_table, engine_clock,
648 graphic_level->SclkFrequency = engine_clock;
669 smu7_get_sleep_divider_id_from_clock(engine_clock,
1464 uint32_t engine_clock,
[all...] |
| amdgpu_ci_smumgr.c | 1626 uint32_t engine_clock,
1637 engine_clock, memory_clock);
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_si_dpm.c | 1855 u32 engine_clock,
4744 u32 engine_clock)
4757 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
5250 u32 engine_clock,
5269 engine_clock, false, ÷rs);
5275 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5292 u32 vco_freq = engine_clock * dividers.post_div;
5308 sclk->sclk_value = engine_clock;
5320 u32 engine_clock,
5326 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| amdgpu_smu.h | 319 uint32_t engine_clock; member in struct:smu_clocks
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