| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_rlc.c | 44 if (adev->gfx.rlc.in_safe_mode)
48 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev))
54 adev->gfx.rlc.funcs->set_safe_mode(adev);
55 adev->gfx.rlc.in_safe_mode = true;
68 if (!(adev->gfx.rlc.in_safe_mode))
72 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev))
78 adev->gfx.rlc.funcs->unset_safe_mode(adev);
79 adev->gfx.rlc.in_safe_mode = false;
102 &adev->gfx.rlc.save_restore_obj,
103 &adev->gfx.rlc.save_restore_gpu_addr
[all...] |
| amdgpu_gfx.c | 36 /* delay 0.1 second to enable gfx off feature */
40 * GPU GFX IP block helpers function.
48 bit += mec * adev->gfx.mec.num_pipe_per_mec
49 * adev->gfx.mec.num_queue_per_pipe;
50 bit += pipe * adev->gfx.mec.num_queue_per_pipe;
59 *queue = bit % adev->gfx.mec.num_queue_per_pipe;
60 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
61 % adev->gfx.mec.num_pipe_per_mec;
62 *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
63 / adev->gfx.mec.num_pipe_per_mec
[all...] |
| amdgpu_gfx_v10_0.c | 45 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
383 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
420 adev->gfx.scratch.num_reg = 8;
421 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
422 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
564 release_firmware(adev->gfx.pfp_fw);
565 adev->gfx.pfp_fw = NULL;
566 release_firmware(adev->gfx.me_fw);
567 adev->gfx.me_fw = NULL
[all...] |
| amdgpu_gfx_v6_0.c | 346 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
349 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
352 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
353 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
354 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
357 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
360 err = amdgpu_ucode_validate(adev->gfx.me_fw);
363 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
364 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
365 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version)
[all...] |
| amdgpu_gfx_v8_0.c | 839 adev->gfx.scratch.num_reg = 8;
840 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
841 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
939 release_firmware(adev->gfx.pfp_fw);
940 adev->gfx.pfp_fw = NULL;
941 release_firmware(adev->gfx.me_fw);
942 adev->gfx.me_fw = NULL;
943 release_firmware(adev->gfx.ce_fw);
944 adev->gfx.ce_fw = NULL
[all...] |
| amdgpu_gfx_v9_0.c | 52 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
877 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs;
940 adev->gfx.scratch.num_reg = 8;
941 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
942 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
1074 release_firmware(adev->gfx.pfp_fw);
1075 adev->gfx.pfp_fw = NULL;
1076 release_firmware(adev->gfx.me_fw);
1077 adev->gfx.me_fw = NULL
[all...] |
| amdgpu_gfx_v7_0.c | 938 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
941 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
946 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
949 err = amdgpu_ucode_validate(adev->gfx.me_fw);
954 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
957 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
962 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
965 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
971 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
974 err = amdgpu_ucode_validate(adev->gfx.mec2_fw)
[all...] |
| amdgpu_discovery.c | 392 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se);
393 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) +
395 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se);
396 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se);
397 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c);
398 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs);
399 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds);
400 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth);
401 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth);
402 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer)
[all...] |
| amdgpu_debugfs.c | 158 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
159 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) {
532 * amdgpu_debugfs_gca_config_read - Read from gfx config data
562 config[no_regs++] = adev->gfx.config.max_shader_engines;
563 config[no_regs++] = adev->gfx.config.max_tile_pipes;
564 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
565 config[no_regs++] = adev->gfx.config.max_sh_per_se;
566 config[no_regs++] = adev->gfx.config.max_backends_per_se;
567 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
568 config[no_regs++] = adev->gfx.config.max_gprs
[all...] |
| amdgpu_amdkfd.c | 121 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
122 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
135 adev->gfx.mec.queue_bitmap,
142 * adev->gfx.mec.num_pipe_per_mec
143 * adev->gfx.mec.num_queue_per_pipe;
354 return adev->gfx.pfp_fw_version;
357 return adev->gfx.me_fw_version;
360 return adev->gfx.ce_fw_version;
363 return adev->gfx.mec_fw_version;
366 return adev->gfx.mec2_fw_version
[all...] |
| amdgpu_amdkfd_gfx_v10.c | 58 config->gb_addr_config = adev->gfx.config.gb_addr_config;
65 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
67 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
71 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
73 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
75 adev->gfx.config.macrotile_mode_array;
77 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
109 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
110 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
118 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe
[all...] |
| amdgpu_kms.c | 238 fw_info->ver = adev->gfx.me_fw_version;
239 fw_info->feature = adev->gfx.me_feature_version;
242 fw_info->ver = adev->gfx.pfp_fw_version;
243 fw_info->feature = adev->gfx.pfp_feature_version;
246 fw_info->ver = adev->gfx.ce_fw_version;
247 fw_info->feature = adev->gfx.ce_feature_version;
250 fw_info->ver = adev->gfx.rlc_fw_version;
251 fw_info->feature = adev->gfx.rlc_feature_version;
254 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
255 fw_info->feature = adev->gfx.rlc_srlc_feature_version
[all...] |
| amdgpu_amdkfd_gfx_v9.c | 65 config->gb_addr_config = adev->gfx.config.gb_addr_config;
67 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
69 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
71 adev->gfx.config.macrotile_mode_array;
73 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
105 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
106 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
114 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe +
158 * need to do this twice, once for gfx and once for mmhub
209 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1
[all...] |
| amdgpu_ucode.c | 105 DRM_DEBUG("GFX\n");
117 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
404 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
405 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
406 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
407 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
408 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
409 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
410 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
411 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version)
[all...] |
| amdgpu_atomfirmware.c | 447 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
448 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
449 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
450 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
451 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
452 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
453 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
454 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
455 adev->gfx.config.gs_prim_buffer_depth =
457 adev->gfx.config.double_offchip_lds_buf
[all...] |
| amdgpu_amdkfd_gfx_v8.c | 57 config->gb_addr_config = adev->gfx.config.gb_addr_config;
58 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
60 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
63 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
65 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
67 adev->gfx.config.macrotile_mode_array;
69 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
102 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
103 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
164 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1
[all...] |
| amdgpu_amdkfd_gfx_v7.c | 100 config->gb_addr_config = adev->gfx.config.gb_addr_config;
101 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
103 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
106 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
108 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
110 adev->gfx.config.macrotile_mode_array;
112 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
145 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
146 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
206 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1
[all...] |
| amdgpu_ctx.c | 89 sched = &adev->gfx.gfx_ring[0].sched;
94 scheds = adev->gfx.compute_sched;
95 num_scheds = adev->gfx.num_compute_sched;
646 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
647 adev->gfx.gfx_sched[i] = &adev->gfx.gfx_ring[i].sched;
648 adev->gfx.num_gfx_sched++;
651 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
652 adev->gfx.compute_sched[i] = &adev->gfx.compute_ring[i].sched
[all...] |
| amdgpu_vcn_v1_0.c | 339 adev->gfx.config.gb_addr_config);
341 adev->gfx.config.gb_addr_config);
343 adev->gfx.config.gb_addr_config);
345 adev->gfx.config.gb_addr_config);
347 adev->gfx.config.gb_addr_config);
349 adev->gfx.config.gb_addr_config);
351 adev->gfx.config.gb_addr_config);
353 adev->gfx.config.gb_addr_config);
355 adev->gfx.config.gb_addr_config);
357 adev->gfx.config.gb_addr_config)
[all...] |
| /src/sys/arch/amiga/stand/dumpfont/ |
| dumpfont.c | 13 #include <graphics/gfx.h>
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| aspeed-bmc-inspur-on5263m5.dts | 122 &gfx {
127 aspeed,external-nodes = <&gfx &lhc>;
|
| aspeed-bmc-intel-s2600wf.dts | 117 &gfx {
122 aspeed,external-nodes = <&gfx &lhc>;
|
| aspeed-bmc-supermicro-x11spi.dts | 122 &gfx {
127 aspeed,external-nodes = <&gfx &lhc>;
|
| /src/sys/arch/sgimips/gio/ |
| gio.c | 183 uint32_t gfx[MAXGFX]; local in function:gio_attach
189 memset(gfx, 0, sizeof(gfx));
226 gfx[ngfx++] = gfx_bases[i].base;
248 if (slot_bases[i].base == gfx[j]) {
284 /* gfx probe */
|
| /src/sys/arch/sgimips/sgimips/ |
| arcemu.c | 214 char gfx[32]; member in struct:arcemu_sgienv
339 extractenv(env, "gfx", sgienv.gfx, sizeof(sgienv.gfx));
395 if (strstr(sgienv.gfx, "dead") != NULL)
432 if (strcasecmp("gfx", var) == 0) {
433 if (sgienv.gfx[0] != '\0')
434 return (sgienv.gfx);
|
