| /src/sys/arch/arm/gemini/ |
| gemini_icu.c | 121 geminiicu_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
124 KASSERT(irqbase == 0 && (irq_mask & sc->sc_enabled_mask) == 0);
125 sc->sc_enabled_mask |= irq_mask;
131 if (irq_mask & sc->sc_level_mask)
133 irq_mask & sc->sc_level_mask);
137 geminiicu_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
142 sc->sc_enabled_mask &= ~irq_mask;
148 if (irq_mask & sc->sc_edge_mask)
150 irq_mask & sc->sc_edge_mask);
195 const uint32_t irq_mask = __BIT(is->is_irq) local in function:geminiicu_establish_irq
[all...] |
| gemini_gpio.c | 111 gpio_pic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
116 gpio->gpio_enable_mask |= irq_mask;
122 if (irq_mask & gpio->gpio_level_mask)
124 irq_mask & gpio->gpio_level_mask);
128 gpio_pic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
133 gpio->gpio_enable_mask &= ~irq_mask;
134 GPIO_WRITE(gpio, GEMINI_GPIO_INTRENB, ~irq_mask);
139 if (irq_mask & gpio->gpio_edge_mask)
141 irq_mask & gpio->gpio_edge_mask);
168 uint32_t irq_mask = __BIT(is->is_irq) local in function:gpio_pic_establish_irq
[all...] |
| /src/sys/arch/arm/marvell/ |
| mvsoc_intr.c | 111 uint32_t irq_mask)
115 read_mlmbreg(MVSOC_MLMB_MLMBICR) & ~irq_mask);
117 read_mlmbreg(MVSOC_MLMB_MLMBIMR) | irq_mask);
123 uint32_t irq_mask)
127 read_mlmbreg(MVSOC_MLMB_MLMBIMR) & ~irq_mask);
|
| mvsocgpp.c | 242 gpio_pic_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
249 irq_mask = irq_mask << mvsocgpp_pic->shift;
251 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(pin)) & ~irq_mask);
252 if (irq_mask & mvsocgpp_pic->edge) {
254 mask |= (irq_mask & mvsocgpp_pic->edge);
257 if (irq_mask & mvsocgpp_pic->level) {
259 mask |= (irq_mask & mvsocgpp_pic->level);
266 gpio_pic_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
272 irq_mask = irq_mask << mvsocgpp_pic->shift
[all...] |
| mv78xx0.c | 137 uint32_t irq_mask)
142 read_mlmbreg(MV78XX0_ICI_IRQIMR(group)) | irq_mask);
147 mv78xx0_pic_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
152 read_mlmbreg(MV78XX0_ICI_IRQIMR(group)) & ~irq_mask);
|
| orion.c | 129 orion_pic_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
133 read_mlmbreg(ORION_MLMB_MIRQIMR) | irq_mask);
138 orion_pic_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
142 read_mlmbreg(ORION_MLMB_MIRQIMR) & ~irq_mask);
|
| kirkwood.c | 168 uint32_t irq_mask)
174 write_mlmbreg(reg, read_mlmbreg(reg) | irq_mask);
180 uint32_t irq_mask)
186 write_mlmbreg(reg, read_mlmbreg(reg) & ~irq_mask);
|
| armadaxp.c | 611 uint32_t irq_mask)
615 while (irq_mask != 0) {
616 n = ffs(irq_mask) - 1;
623 irq_mask &= ~__BIT(n);
629 uint32_t irq_mask)
633 while (irq_mask != 0) {
634 n = ffs(irq_mask) - 1;
638 irq_mask &= ~__BIT(n);
732 uint32_t irq_mask)
739 reg |= irq_mask;
[all...] |
| /src/sys/arch/arm/imx/ |
| imx31_gpio.c | 97 gpio_pic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
102 gpio->gpio_enable_mask |= irq_mask;
107 if (irq_mask & gpio->gpio_level_mask)
108 GPIO_WRITE(gpio, GPIO_ISR, irq_mask);
113 gpio_pic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
118 gpio->gpio_enable_mask &= ~irq_mask;
172 uint32_t irq_mask = __BIT(is->is_irq); local in function:gpio_pic_establish_irq
180 gpio->gpio_enable_mask &= ~irq_mask;
182 GPIO_WRITE(gpio, GPIO_ISR, irq_mask);
204 v &= ~irq_mask;
[all...] |
| imx31_icu.c | 84 avic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
89 INTC_WRITE(avic, IMX31_INTENABLEL, irq_mask);
91 INTC_WRITE(avic, IMX31_INTENABLEH, irq_mask);
94 while ((irq = ffs(irq_mask)) != 0) {
97 irq_mask >>= irq;
104 avic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
109 INTC_WRITE(avic, IMX31_INTDISABLEL, irq_mask);
111 INTC_WRITE(avic, IMX31_INTDISABLEH, irq_mask);
114 while ((irq = ffs(irq_mask)) != 0) {
117 irq_mask >>= irq
[all...] |
| imxgpio.c | 89 imxgpio_pic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
94 gpio->gpio_enable_mask |= irq_mask;
96 GPIO_WRITE(gpio, GPIO_ISR, irq_mask);
101 imxgpio_pic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
106 gpio->gpio_enable_mask &= ~irq_mask;
180 uint32_t irq_mask = __BIT(is->is_irq); local in function:imxgpio_pic_establish_irq
188 gpio->gpio_enable_mask &= ~irq_mask;
189 GPIO_WRITE(gpio, GPIO_ISR, irq_mask);
211 v &= ~irq_mask;
218 gpio->gpio_edge_mask |= irq_mask;
[all...] |
| imx51_tzic.c | 168 tzic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
173 KASSERT((irq_mask & tzic->sc_enabled_mask[group]) == 0);
175 tzic->sc_enabled_mask[group] |= irq_mask;
176 INTC_WRITE(tzic, TZIC_ENSET(group), irq_mask);
180 tzic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
185 tzic->sc_enabled_mask[group] &= ~irq_mask;
187 INTC_WRITE(tzic, TZIC_ENCLEAR(group), irq_mask);
|
| imx23_icoll.c | 187 icoll_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
193 b = ffs(irq_mask);
197 irq_mask &= ~(1<<b);
204 icoll_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
210 b = ffs(irq_mask);
214 irq_mask &= ~(1<<b);
|
| /src/sys/arch/arm/ti/ |
| ti_omapintc.c | 108 omap2icu_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
112 KASSERT((irq_mask & sc->sc_enabled_irqs[group]) == 0);
113 sc->sc_enabled_irqs[group] |= irq_mask;
114 INTC_WRITE(sc, group, INTC_MIR_CLEAR, irq_mask);
121 omap2icu_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
126 INTC_WRITE(sc, group, INTC_MIR_SET, irq_mask);
127 sc->sc_enabled_irqs[group] &= ~irq_mask;
|
| /src/sys/arch/acorn32/podulebus/ |
| netslot.c | 124 podule->irq_mask = *address;
129 if (podule->irq_mask == 0)
130 podule->irq_mask = 0x01;
140 podule->irq_mask = 0x01;
|
| rapide.c | 157 u_int irq_mask; member in struct:__anon63076f770108
242 sc->sc_podule->irq_mask = IRQ_MASK;
290 rcp->rc_irqmask = rapide_info[channel].irq_mask;
|
| simide.c | 123 u_int irq_mask; member in struct:__anonb01bb07d0108
210 sc->sc_podule->irq_mask = STATUS_IRQ;
281 scp->sc_irqmask = simide_info[channel].irq_mask;
|
| podulebus.c | 160 printf("irq_mask=%02x ", podule->irq_mask);
375 podule->irq_mask = address[48];
376 if (podule->irq_mask == 0)
377 podule->irq_mask = 0x01;
385 podule->irq_mask = 0x01;
|
| /src/sys/arch/epoc32/windermere/ |
| windermere.c | 215 uint32_t irq_mask)
220 *(intr + INTENS) = irq_mask;
221 pic_mask |= irq_mask;
227 uint32_t irq_mask)
232 *(intr + INTENC) = irq_mask;
233 pic_mask &= ~irq_mask;
|
| /src/sys/arch/mips/cavium/ |
| octeon_intr.c | 371 const uint64_t irq_mask = __BIT(irq % 64); local in function:octeon_intr_establish
376 cpu->cpu_ip2_enable[bank] |= irq_mask;
383 cpu->cpu_ip3_enable[bank] |= irq_mask;
390 cpu->cpu_ip3_enable[bank] |= irq_mask;
400 cpu->cpu_ip4_enable[bank] |= irq_mask;
407 cpu->cpu_ip4_enable[bank] |= irq_mask;
434 const uint64_t irq_mask = ~__BIT(irq % 64); local in function:octeon_intr_disestablish
439 cpu->cpu_ip2_enable[bank] &= ~irq_mask;
448 cpu->cpu_ip3_enable[bank] &= ~irq_mask;
459 cpu->cpu_ip4_enable[bank] &= ~irq_mask;
[all...] |
| /src/sys/arch/arm/clps711x/ |
| clpssoc.c | 206 uint32_t irq_mask)
209 INTMR |= irq_mask;
214 clpssoc_pic_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
217 INTMR &= ~irq_mask;
|
| /src/sys/external/bsd/drm/dist/shared-core/ |
| radeon_irq.c | 141 u32 irq_mask = RADEON_SW_INT_TEST; local in function:radeon_acknowledge_irqs
161 irq_mask |= R500_DISPLAY_INT_STATUS;
163 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
165 irqs &= irq_mask;
|
| /src/sys/arch/arm/broadcom/ |
| bcm2835_intr.c | 443 uint32_t irq_mask)
446 write_bcm2835reg(BCM2835_INTC_ENABLEBASE + (irqbase >> 3), irq_mask);
452 uint32_t irq_mask)
455 write_bcm2835reg(BCM2835_INTC_DISABLEBASE + (irqbase >> 3), irq_mask);
694 uint32_t irq_mask)
703 if (irq_mask & BCM2836MP_TIMER_IRQS) {
704 uint32_t mask = __SHIFTOUT(irq_mask, BCM2836MP_TIMER_IRQS);
716 if (irq_mask & BCM2836MP_MAILBOX_IRQS) {
717 uint32_t mask = __SHIFTOUT(irq_mask, BCM2836MP_MAILBOX_IRQS);
729 if (irq_mask & BCM2836MP_PMU_IRQ)
[all...] |
| /src/sys/arch/acorn32/include/ |
| podulebus_machdep.h | 62 u_int irq_mask; member in struct:__anon529cc25c0108
|
| /src/sys/external/bsd/drm2/dist/drm/vmwgfx/ |
| vmwgfx_irq.c | 112 masked_status = status & READ_ONCE(dev_priv->irq_mask);
338 dev_priv->irq_mask |= flag;
339 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
349 dev_priv->irq_mask &= ~flag;
350 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
|
