| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/ |
| bcm958742t.dts | 43 enet-phy-lane-swap;
|
| bcm958742k.dts | 43 enet-phy-lane-swap;
|
| /src/sys/arch/arm/rockchip/ |
| rk_tcphy.c | 72 #define TX_TXCC_MGNFS_MULT_000(lane) ((0x4050 | ((lane) << 9)) << 2)
73 #define XCVR_DIAG_BIDI_CTRL(lane) ((0x40e8 | ((lane) << 9)) << 2)
74 #define XCVR_DIAG_LANE_FCM_EN_MGN(lane) ((0x40f2 | ((lane) << 9)) << 2)
75 #define TX_PSC_A0(lane) ((0x4100 | ((lane) << 9)) << 2)
76 #define TX_PSC_A1(lane) ((0x4101 | ((lane) << 9)) << 2
[all...] |
| rk3399_pcie_phy.c | 120 uint8_t * const lane = priv; local
122 // device_printf(dev, "%s %u %u\n", __func__, *lane, enable);
125 rkpcie_phy_poweron(sc, *lane);
126 sc->sc_phys_on |= 1U << *lane;
129 sc->sc_phys_on &= ~(1U << *lane);
202 rkpcie_phy_poweron(struct rkpciephy_softc *sc, u_int lane)
219 RK3399_TX_ELEC_IDLE_OFF_MASK << lane | 0);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dp_link_training.c | 48 int lane; local
52 for (lane = 0; lane < intel_dp->lane_count; lane++) {
53 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
54 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
70 for (lane = 0; lane < 4; lane++)
71 intel_dp->train_set[lane] = v | p
124 int lane; local
[all...] |
| intel_dpio_phy.c | 47 * houses a common lane part which contains the PLL and other common
48 * logic. CH0 common lane also contains the IOSF-SB logic for the
63 * Additionally the PHY also contains an AUX lane with AUX blocks
69 * Generally on VLV/CHV the common lane corresponds to the pipe and
284 * can read only lane registers and we pick lanes 0/1 for that.
602 int lane; local
606 for (lane = 0; lane < 4; lane++) {
607 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
628 int lane; local
[all...] |
| icl_dsi.c | 213 int lane; local
258 for (lane = 0; lane <= 3; lane++) {
260 tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
266 I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
398 int lane; local
405 for (lane = 0; lane <= 3; lane++)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_link_dp.c | 175 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
185 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
245 uint32_t lane; local
278 for (lane = 0; lane <
279 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
281 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
282 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
283 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
284 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS)
354 uint32_t lane; local
369 uint32_t lane; local
387 uint32_t lane; local
437 uint32_t lane; local
541 uint32_t lane; local
648 uint32_t lane; local
728 uint32_t lane; local
750 uint32_t lane; local
1107 uint32_t lane; local
1796 uint32_t lane; local
2507 unsigned int lane; local
3797 unsigned int lane; local
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_dp_helper.c | 62 int lane)
64 int i = DP_LANE0_1_STATUS + (lane >> 1);
65 int s = (lane & 1) * 4;
75 int lane; local
81 for (lane = 0; lane < lane_count; lane++) {
82 lane_status = dp_get_lane_status(link_status, lane);
93 int lane; local
96 for (lane = 0; lane < lane_count; lane++)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_atombios_dp.c | 217 int lane; local
219 for (lane = 0; lane < lane_count; lane++) {
220 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
221 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
223 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
224 lane,
244 for (lane = 0; lane < 4; lane++
[all...] |
| /src/sys/external/isc/libsodium/dist/src/libsodium/crypto_pwhash/argon2/ |
| argon2-fill-block-avx2.c | 112 input_block.v[1] = position->lane;
179 curr_offset = position.lane * instance->lane_length +
183 /* Last block in this lane */
211 /* 1.2.2 Computing the lane of the reference block */
216 ref_lane = position.lane;
220 * lane.
224 ref_lane == position.lane);
|
| argon2-fill-block-avx512f.c | 117 input_block.v[1] = position->lane;
184 curr_offset = position.lane * instance->lane_length +
188 /* Last block in this lane */
216 /* 1.2.2 Computing the lane of the reference block */
221 ref_lane = position.lane;
225 * lane.
229 ref_lane == position.lane);
|
| argon2-fill-block-ref.c | 123 input_block.v[1] = position->lane;
177 curr_offset = position.lane * instance->lane_length +
181 /* Last block in this lane */
206 /* 1.2.2 Computing the lane of the reference block */
211 ref_lane = position.lane;
215 * lane.
219 ref_lane == position.lane);
|
| argon2-fill-block-ssse3.c | 111 input_block.v[1] = position->lane;
178 curr_offset = position.lane * instance->lane_length +
182 /* Last block in this lane */
210 /* 1.2.2 Computing the lane of the reference block */
215 ref_lane = position.lane;
219 * lane.
223 ref_lane == position.lane);
|
| argon2-core.h | 115 uint32_t lane; member in struct:Argon2_position_t
130 * Computes absolute position of reference block in the lane following a skewed
135 * @param same_lane Indicates if the block will be taken from the current lane.
145 * This lane : all already finished segments plus already constructed
149 * This lane : (SYNC_POINTS - 1) last segments plus already constructed
165 /* The same lane => add current segment */
233 * Function creates first 2 blocks per lane
242 * two blocks. Returns the pointer to the main memory with 2 blocks per lane
258 * XORing the last block of each lane, hashing it, making the tag. Deallocates
291 * blocks in each lane
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
| nouveau_nvkm_engine_disp_dp.c | 93 u8 lane = (lt->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; local
95 u8 lpre = (lane & 0x0c) >> 2;
96 u8 lvsw = (lane & 0x03) >> 0;
114 OUTP_TRACE(&dp->outp, "config lane %d %02x %02x",
180 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; local
181 if (!(lane & DPCD_LS02_LANE0_CR_DONE))
183 if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
184 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
208 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; local
209 if (!(lane & DPCD_LS02_LANE0_CR_DONE))
494 u8 lane = (stat[i >> 1] >> ((i & 1) * 4)) & 0x0f; local
[all...] |
| /src/sys/arch/arm/nvidia/ |
| tegra210_xusbpad.c | 663 tegra210_xusbpad_find_func(const struct tegra210_xusbpad_lane *lane,
666 for (int n = 0; n < lane->nfuncs; n++)
667 if (strcmp(lane->funcs[n], func) == 0)
685 const struct tegra210_xusbpad_lane *lane; local
700 lane = tegra210_xusbpad_find_lane(name);
701 if (lane == NULL) {
702 aprint_error_dev(sc->sc_dev, "unsupported lane '%s'\n", name);
705 func = tegra210_xusbpad_find_func(lane, function);
711 aprint_normal_dev(sc->sc_dev, "lane %s: set func %s\n", name, function);
712 SETCLR4(sc, lane->reg, __SHIFTIN(func, lane->mask), lane->mask)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_atombios_dp.c | 275 int lane; local
277 for (lane = 0; lane < lane_count; lane++) {
278 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
279 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
281 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
282 lane,
302 for (lane = 0; lane < 4; lane++
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_link_encoder.c | 1089 * by checking lane count that has been set
1119 int32_t lane = 0; local
1135 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1136 /* translate lane settings */
1139 link_settings->lane_settings[lane].VOLTAGE_SWING;
1141 link_settings->lane_settings[lane].PRE_EMPHASIS;
1149 link_settings->lane_settings[lane].POST_CURSOR2;
1152 cntl.lane_select = lane;
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_link_encoder.c | 1054 * by checking lane count that has been set
1085 int32_t lane = 0; local
1101 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1102 /* translate lane settings */
1105 link_settings->lane_settings[lane].VOLTAGE_SWING;
1107 link_settings->lane_settings[lane].PRE_EMPHASIS;
1115 link_settings->lane_settings[lane].POST_CURSOR2;
1118 cntl.lane_select = lane;
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/northstar2/ |
| ns2-svk.dts | 187 enet-phy-lane-swap;
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/lpc/ |
| lpc4350-hitex-eval.dts | 361 mpmc,byte-lane-low;
398 mpmc,byte-lane-low;
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/usb/ |
| pd.h | 372 * <3> :: USB lanes supported (0b == one lane, 1b == two lanes)
406 #define VDO_ACABLE2(mtemp, stemp, u3p, trans, phy, ele, u4, hops, u2, u32, lane, iso, gen) \
409 | ((hops) & 0x3) << 6 | (u2) << 5 | (u32) << 4 | (lane) << 3 \
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_reg.h | 1713 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1714 (lane) * 0x200 + (offset))
1716 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1717 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1718 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1719 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| cwsr_trap_handler_gfx9.asm | 981 for var lane = 0; lane < 4; ++ lane
982 v_readlane_b32 s[lane], v, s4
|
