| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_timing_generator.c | 403 offset = mmD2VGA_CONTROL - mmD1VGA_CONTROL;
406 offset = mmD3VGA_CONTROL - mmD1VGA_CONTROL;
409 offset = mmD4VGA_CONTROL - mmD1VGA_CONTROL;
412 offset = mmD5VGA_CONTROL - mmD1VGA_CONTROL;
415 offset = mmD6VGA_CONTROL - mmD1VGA_CONTROL;
421 value = dm_read_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset);
429 dm_write_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset, value);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_vi.c | 393 d1vga_control = RREG32(mmD1VGA_CONTROL);
403 WREG32(mmD1VGA_CONTROL,
419 WREG32(mmD1VGA_CONTROL, d1vga_control);
|
| amdgpu_cik.c | 909 d1vga_control = RREG32(mmD1VGA_CONTROL);
919 WREG32(mmD1VGA_CONTROL,
935 WREG32(mmD1VGA_CONTROL, d1vga_control);
|
| amdgpu_gmc_v10_0.c | 743 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
|
| amdgpu_gmc_v6_0.c | 824 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
|
| amdgpu_gmc_v7_0.c | 982 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
|
| amdgpu_gmc_v9_0.c | 1045 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
|
| amdgpu_gmc_v8_0.c | 1094 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
|
| amdgpu_dce_v10_0.c | 1818 mmD1VGA_CONTROL,
|
| amdgpu_dce_v11_0.c | 1860 mmD1VGA_CONTROL,
|
| amdgpu_dce_v6_0.c | 1784 mmD1VGA_CONTROL,
|
| amdgpu_dce_v8_0.c | 1747 mmD1VGA_CONTROL,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_timing_generator.c | 1817 addr = mmD1VGA_CONTROL;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/ |
| dce_6_0_d.h | 1043 #define mmD1VGA_CONTROL 0x00CC
|
| dce_8_0_d.h | 5146 #define mmD1VGA_CONTROL 0xcc
|
| dce_10_0_d.h | 6029 #define mmD1VGA_CONTROL 0xcc
|
| dce_11_0_d.h | 6106 #define mmD1VGA_CONTROL 0xcc
|
| dce_11_2_d.h | 7780 #define mmD1VGA_CONTROL 0xcc
|
| dce_12_0_offset.h | 576 #define mmD1VGA_CONTROL 0x000c
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/ |
| dcn_1_0_offset.h | 410 #define mmD1VGA_CONTROL 0x000c
[all...] |
| dcn_2_1_0_offset.h | 114 #define mmD1VGA_CONTROL 0x000c
[all...] |
| dcn_2_0_0_offset.h | 54 #define mmD1VGA_CONTROL 0x000c
[all...] |
