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    Searched refs:mmUVD_CGC_CTRL (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h 36 #define mmUVD_CGC_CTRL 0x3D2C
uvd_4_2_d.h 46 #define mmUVD_CGC_CTRL 0x3d2c
uvd_5_0_d.h 52 #define mmUVD_CGC_CTRL 0x3d2c
uvd_6_0_d.h 68 #define mmUVD_CGC_CTRL 0x3d2c
uvd_7_0_offset.h 148 #define mmUVD_CGC_CTRL 0x052c
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v5_0.c 657 data = RREG32(mmUVD_CGC_CTRL);
696 WREG32(mmUVD_CGC_CTRL, data);
751 orig = data = RREG32(mmUVD_CGC_CTRL);
754 WREG32(mmUVD_CGC_CTRL, data);
760 orig = data = RREG32(mmUVD_CGC_CTRL);
763 WREG32(mmUVD_CGC_CTRL, data);
828 data = RREG32(mmUVD_CGC_CTRL);
amdgpu_uvd_v4_2.c 591 orig = data = RREG32(mmUVD_CGC_CTRL);
594 WREG32(mmUVD_CGC_CTRL, data);
600 orig = data = RREG32(mmUVD_CGC_CTRL);
603 WREG32(mmUVD_CGC_CTRL, data);
614 tmp = RREG32(mmUVD_CGC_CTRL);
630 WREG32(mmUVD_CGC_CTRL, tmp);
amdgpu_uvd_v6_0.c 1312 data = RREG32(mmUVD_CGC_CTRL);
1352 WREG32(mmUVD_CGC_CTRL, data);
1409 orig = data = RREG32(mmUVD_CGC_CTRL);
1412 WREG32(mmUVD_CGC_CTRL, data);
1418 orig = data = RREG32(mmUVD_CGC_CTRL);
1421 WREG32(mmUVD_CGC_CTRL, data);
1491 data = RREG32(mmUVD_CGC_CTRL);
amdgpu_vcn_v1_0.c 465 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
473 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
498 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
519 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
590 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
597 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
599 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
620 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
678 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
amdgpu_vcn_v2_0.c 459 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
466 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
491 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
512 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
589 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
617 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
624 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
626 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
647 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
amdgpu_vcn_v2_5.c 546 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
553 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
581 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
602 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
680 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
711 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
718 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
720 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
740 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
amdgpu_uvd_v7_0.c 851 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL),
964 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
1592 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1638 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 310 #define mmUVD_CGC_CTRL 0x052c
vcn_2_0_0_offset.h 510 #define mmUVD_CGC_CTRL 0x01ec
vcn_2_5_offset.h 503 #define mmUVD_CGC_CTRL 0x008a

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