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    Searched refs:mmUVD_CGC_GATE (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h 37 #define mmUVD_CGC_GATE 0x3D2A
uvd_4_2_d.h 44 #define mmUVD_CGC_GATE 0x3d2a
uvd_5_0_d.h 50 #define mmUVD_CGC_GATE 0x3d2a
uvd_6_0_d.h 66 #define mmUVD_CGC_GATE 0x3d2a
uvd_7_0_offset.h 146 #define mmUVD_CGC_GATE 0x052a
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v5_0.c 612 data3 = RREG32(mmUVD_CGC_GATE);
650 WREG32(mmUVD_CGC_GATE, data3);
705 data = RREG32(mmUVD_CGC_GATE);
736 WREG32(mmUVD_CGC_GATE, data);
amdgpu_uvd_v6_0.c 624 data = RREG32(mmUVD_CGC_GATE);
692 WREG32(mmUVD_CGC_GATE, data);
1258 data3 = RREG32(mmUVD_CGC_GATE);
1305 WREG32(mmUVD_CGC_GATE, data3);
1361 data = RREG32(mmUVD_CGC_GATE);
1394 WREG32(mmUVD_CGC_GATE, data);
amdgpu_vcn_v2_5.c 555 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);
577 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);
579 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, ret);
684 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
amdgpu_uvd_v7_0.c 1639 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1648 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1681 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
amdgpu_vcn_v1_0.c 475 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
496 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
681 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
amdgpu_vcn_v2_0.c 468 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
489 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
593 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
amdgpu_uvd_v4_2.c 273 WREG32(mmUVD_CGC_GATE, 0);
amdgpu_si.c 113 mmUVD_CGC_GATE, 0x00000008, 0x00000000,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 306 #define mmUVD_CGC_GATE 0x052a
vcn_2_0_0_offset.h 506 #define mmUVD_CGC_GATE 0x01ea
vcn_2_5_offset.h 499 #define mmUVD_CGC_GATE 0x0088

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