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Searched refs:mmUVD_CONTEXT_ID (Results 1 - 13 of 13) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h	`40 #define mmUVD_CONTEXT_ID 0x3DBD`
uvd_4_2_d.h	`83 #define mmUVD_CONTEXT_ID 0x3dbd`
uvd_5_0_d.h	`89 #define mmUVD_CONTEXT_ID 0x3dbd`
uvd_6_0_d.h	`105 #define mmUVD_CONTEXT_ID 0x3dbd`
uvd_7_0_offset.h	`218 #define mmUVD_CONTEXT_ID 0x05bd`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c	`456 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 487 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 492 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 496 tmp = RREG32(mmUVD_CONTEXT_ID);`
amdgpu_uvd_v5_0.c	`473 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 504 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 508 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 512 tmp = RREG32(mmUVD_CONTEXT_ID);`
amdgpu_uvd_v6_0.c	`906 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 967 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 972 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 976 tmp = RREG32(mmUVD_CONTEXT_ID);`
amdgpu_uvd_v7_0.c	`1170 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1238 WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD); 1244 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1248 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);`
amdgpu_vcn_v1_0.c	`1469 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`406 #define mmUVD_CONTEXT_ID 0x05bd`
vcn_2_0_0_offset.h	`728 #define mmUVD_CONTEXT_ID 0x027d`
vcn_2_5_offset.h	`547 #define mmUVD_CONTEXT_ID 0x00a7`

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