NetBSD Cross-Reference & Source Code Search Engine

Home	Sort by: relevance \| last modified time \| path

Full Search

in project(s):

Definition

Symbol

File Path

History

| | Help

Searched refs:mmUVD_GPCOM_VCPU_DATA0 (Results 1 - 16 of 16) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h	`45 #define mmUVD_GPCOM_VCPU_DATA0 0x3BC4`
uvd_4_2_d.h	`33 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4`
uvd_5_0_d.h	`33 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4`
uvd_6_0_d.h	`33 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4`
uvd_7_0_offset.h	`58 #define mmUVD_GPCOM_VCPU_DATA0 0x03c4`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v6_0.c	`908 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 915 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 1039 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 1052 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 1067 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));`
amdgpu_vcn_v1_0.c	`144 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 1430 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1472 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1482 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1530 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1564 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));`
amdgpu_uvd_v4_2.c	`458 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 465 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));`
amdgpu_uvd_v5_0.c	`475 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 482 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));`
amdgpu_uvd_v7_0.c	`1173 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1183 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1348 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1364 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));`
amdgpu_uvd.c	`925 case mmUVD_GPCOM_VCPU_DATA0:`
amdgpu_vcn_v2_0.c	`153 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);`
amdgpu_vcn_v2_5.c	`186 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA0);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`142 #define mmUVD_GPCOM_VCPU_DATA0 0x03c4`
vcn_2_0_0_offset.h	`814 #define mmUVD_GPCOM_VCPU_DATA0 0x0584`
vcn_2_5_offset.h	`515 #define mmUVD_GPCOM_VCPU_DATA0 0x0090`

Completed in 37 milliseconds