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Searched refs:mmUVD_JRBC_RB_WPTR (Results 1 - 8 of 8) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_jpeg_v2_5.c	`347 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0); 350 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR); 415 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR); 433 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));`
amdgpu_jpeg_v1_0.c	`157 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 171 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 530 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); 535 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);`
amdgpu_jpeg_v2_0.c	`370 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); 373 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 436 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 454 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));`
amdgpu_vcn_v1_0.c	`1179 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1314 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_7_0_offset.h	`128 #define mmUVD_JRBC_RB_WPTR 0x0509`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`264 #define mmUVD_JRBC_RB_WPTR 0x0509`
vcn_2_0_0_offset.h	`124 #define mmUVD_JRBC_RB_WPTR 0x0100`
vcn_2_5_offset.h	`139 #define mmUVD_JRBC_RB_WPTR 0x0100`

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