HomeSort by: relevance | last modified time | path
    Searched refs:mmUVD_LMI_CTRL (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h 49 #define mmUVD_LMI_CTRL 0x3D66
uvd_4_2_d.h 51 #define mmUVD_LMI_CTRL 0x3d66
uvd_5_0_d.h 57 #define mmUVD_LMI_CTRL 0x3d66
uvd_6_0_d.h 73 #define mmUVD_LMI_CTRL 0x3d66
uvd_7_0_offset.h 158 #define mmUVD_LMI_CTRL 0x0566
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 338 #define mmUVD_LMI_CTRL 0x0566
vcn_2_0_0_offset.h 564 #define mmUVD_LMI_CTRL 0x0226
vcn_2_5_offset.h 961 #define mmUVD_LMI_CTRL 0x04a8
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c 808 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
809 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
990 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
1044 /* setup mmUVD_LMI_CTRL */
1045 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
amdgpu_vcn_v2_0.c 780 /* setup mmUVD_LMI_CTRL */
790 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
906 /* setup mmUVD_LMI_CTRL */
907 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
908 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
amdgpu_vcn_v2_5.c 788 /* setup mmUVD_LMI_CTRL */
798 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
932 /* setup mmUVD_LMI_CTRL */
933 tmp = RREG32_SOC15(UVD, i, mmUVD_LMI_CTRL);
935 WREG32_SOC15(UVD, i, mmUVD_LMI_CTRL, tmp | 0x8|
amdgpu_uvd_v4_2.c 293 WREG32(mmUVD_LMI_CTRL, 0x203108);
amdgpu_uvd_v5_0.c 334 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
amdgpu_uvd_v7_0.c 875 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),
990 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,
amdgpu_uvd_v6_0.c 745 WREG32(mmUVD_LMI_CTRL,

Completed in 28 milliseconds