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    Searched refs:mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 254 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x0504
vcn_2_0_0_offset.h 250 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x0167
vcn_2_5_offset.h 265 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x0167
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_jpeg_v2_5.c 344 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
amdgpu_jpeg_v1_0.c 528 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
amdgpu_jpeg_v2_0.c 367 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
amdgpu_vcn_v1_0.c 1311 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,

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