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    Searched refs:mmUVD_LMI_JRBC_RB_VMID (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 262 #define mmUVD_LMI_JRBC_RB_VMID 0x0508
vcn_2_0_0_offset.h 220 #define mmUVD_LMI_JRBC_RB_VMID 0x0150
vcn_2_5_offset.h 235 #define mmUVD_LMI_JRBC_RB_VMID 0x0150
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_jpeg_v2_5.c 340 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0);
amdgpu_jpeg_v1_0.c 524 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
amdgpu_jpeg_v2_0.c 363 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
amdgpu_vcn_v1_0.c 1305 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);

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