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    Searched refs:mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_5_0_d.h 43 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x3c66
uvd_6_0_d.h 54 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x3c66
uvd_7_0_offset.h 112 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0466
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 238 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0466
vcn_2_0_0_offset.h 956 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0626
vcn_2_5_offset.h 857 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0435
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v5_0.c 539 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
amdgpu_uvd_v6_0.c 1008 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
amdgpu_uvd_v7_0.c 1313 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
amdgpu_vcn_v1_0.c 1516 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));

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