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Searched refs:mmUVD_LMI_RBC_IB_64BIT_BAR_LOW (Results 1 - 10 of 10) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_5_0_d.h	`42 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67`
uvd_6_0_d.h	`53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67`
uvd_7_0_offset.h	`114 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0467`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`240 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0467`
vcn_2_0_0_offset.h	`958 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0627`
vcn_2_5_offset.h	`855 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0434`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v5_0.c	`537 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));`
amdgpu_uvd_v6_0.c	`1006 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));`
amdgpu_uvd_v7_0.c	`1310 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));`
amdgpu_vcn_v1_0.c	`1513 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));`

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