HomeSort by: relevance | last modified time | path
    Searched refs:mmUVD_LMI_SWAP_CNTL (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h 53 #define mmUVD_LMI_SWAP_CNTL 0x3D6D
uvd_4_2_d.h 53 #define mmUVD_LMI_SWAP_CNTL 0x3d6d
uvd_5_0_d.h 59 #define mmUVD_LMI_SWAP_CNTL 0x3d6d
uvd_6_0_d.h 75 #define mmUVD_LMI_SWAP_CNTL 0x3d6d
uvd_7_0_offset.h 162 #define mmUVD_LMI_SWAP_CNTL 0x056d
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 344 #define mmUVD_LMI_SWAP_CNTL 0x056d
vcn_2_0_0_offset.h 576 #define mmUVD_LMI_SWAP_CNTL 0x022d
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c 290 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
amdgpu_uvd_v5_0.c 342 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
amdgpu_vcn_v1_0.c 819 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
1004 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
amdgpu_uvd_v6_0.c 758 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
amdgpu_uvd_v7_0.c 1003 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
amdgpu_vcn_v2_0.c 961 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);

Completed in 23 milliseconds