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    Searched refs:mmUVD_MASTINT_EN (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h 54 #define mmUVD_MASTINT_EN 0x3D40
uvd_4_2_d.h 49 #define mmUVD_MASTINT_EN 0x3d40
uvd_5_0_d.h 55 #define mmUVD_MASTINT_EN 0x3d40
uvd_6_0_d.h 71 #define mmUVD_MASTINT_EN 0x3d40
uvd_7_0_offset.h 154 #define mmUVD_MASTINT_EN 0x0540
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c 283 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
348 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
amdgpu_uvd_v5_0.c 315 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
392 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
amdgpu_uvd_v7_0.c 855 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
892 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
968 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
1059 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
amdgpu_vcn_v1_0.c 804 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
894 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
986 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
1040 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
amdgpu_vcn_v2_0.c 778 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
834 UVD, 0, mmUVD_MASTINT_EN),
903 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
993 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
amdgpu_vcn_v2_5.c 786 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
846 UVD, 0, mmUVD_MASTINT_EN),
929 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 0,
1024 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
amdgpu_uvd_v6_0.c 808 WREG32_P(mmUVD_MASTINT_EN,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 332 #define mmUVD_MASTINT_EN 0x0540
vcn_2_0_0_offset.h 540 #define mmUVD_MASTINT_EN 0x0200
vcn_2_5_offset.h 535 #define mmUVD_MASTINT_EN 0x00a1

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