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Searched refs:mmUVD_MPC_SET_MUXA0 (Results 1 - 15 of 15) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h	`58 #define mmUVD_MPC_SET_MUXA0 0x3D79`
uvd_4_2_d.h	`56 #define mmUVD_MPC_SET_MUXA0 0x3d79`
uvd_5_0_d.h	`62 #define mmUVD_MPC_SET_MUXA0 0x3d79`
uvd_6_0_d.h	`78 #define mmUVD_MPC_SET_MUXA0 0x3d79`
uvd_7_0_offset.h	`166 #define mmUVD_MPC_SET_MUXA0 0x0579`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`348 #define mmUVD_MPC_SET_MUXA0 0x0579`
vcn_2_0_0_offset.h	`598 #define mmUVD_MPC_SET_MUXA0 0x0239`
vcn_2_5_offset.h	`763 #define mmUVD_MPC_SET_MUXA0 0x02ce`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c	`298 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);`
amdgpu_uvd_v5_0.c	`345 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);`
amdgpu_vcn_v1_0.c	`826 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 1009 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0,`
amdgpu_vcn_v2_0.c	`797 UVD, 0, mmUVD_MPC_SET_MUXA0), 921 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,`
amdgpu_vcn_v2_5.c	`805 UVD, 0, mmUVD_MPC_SET_MUXA0), 948 WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXA0,`
amdgpu_uvd_v6_0.c	`761 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);`
amdgpu_uvd_v7_0.c	`1006 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040);`

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