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Searched refs:mmUVD_MPC_SET_MUXB0 (Results 1 - 15 of 15) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h	`60 #define mmUVD_MPC_SET_MUXB0 0x3D7B`
uvd_4_2_d.h	`58 #define mmUVD_MPC_SET_MUXB0 0x3d7b`
uvd_5_0_d.h	`64 #define mmUVD_MPC_SET_MUXB0 0x3d7b`
uvd_6_0_d.h	`80 #define mmUVD_MPC_SET_MUXB0 0x3d7b`
uvd_7_0_offset.h	`170 #define mmUVD_MPC_SET_MUXB0 0x057b`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`352 #define mmUVD_MPC_SET_MUXB0 0x057b`
vcn_2_0_0_offset.h	`602 #define mmUVD_MPC_SET_MUXB0 0x023b`
vcn_2_5_offset.h	`767 #define mmUVD_MPC_SET_MUXB0 0x02d0`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c	`300 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);`
amdgpu_uvd_v5_0.c	`347 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);`
amdgpu_vcn_v1_0.c	`832 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 1015 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0,`
amdgpu_vcn_v2_0.c	`804 UVD, 0, mmUVD_MPC_SET_MUXB0), 928 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,`
amdgpu_vcn_v2_5.c	`812 UVD, 0, mmUVD_MPC_SET_MUXB0), 955 WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXB0,`
amdgpu_uvd_v6_0.c	`763 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);`
amdgpu_uvd_v7_0.c	`1008 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040);`

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