| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/ |
| uvd_4_0_d.h | 67 #define mmUVD_POWER_STATUS 0x38FC
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| uvd_4_2_d.h | 93 #define mmUVD_POWER_STATUS 0x38fc
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| uvd_5_0_d.h | 105 #define mmUVD_POWER_STATUS 0x38c4
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| uvd_6_0_d.h | 121 #define mmUVD_POWER_STATUS 0x38c4
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| uvd_7_0_offset.h | 30 #define mmUVD_POWER_STATUS 0x00c4
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_vcn_v1_0.c | 728 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
733 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
743 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
746 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
971 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
974 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
1168 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1185 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1190 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1230 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
[all...] |
| amdgpu_vcn_v2_0.c | 701 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
707 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
717 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
720 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
758 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
761 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
1048 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1061 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1065 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1155 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1
[all...] |
| amdgpu_vcn_v2_5.c | 763 WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), 1,
766 tmp = RREG32_SOC15(UVD, inst_idx, mmUVD_POWER_STATUS);
769 WREG32_SOC15(UVD, inst_idx, mmUVD_POWER_STATUS, tmp);
907 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,
1278 SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS, 1,
1291 SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS, 1,
1295 WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), 0,
1358 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS),
1385 SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS, 0x1,
1416 SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS,
[all...] |
| amdgpu_uvd_v5_0.c | 306 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
|
| amdgpu_uvd_v6_0.c | 713 WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1459 WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
|
| amdgpu_uvd_v7_0.c | 949 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
1741 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/ |
| vcn_1_0_offset.h | 34 #define mmUVD_POWER_STATUS 0x00c4
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| vcn_2_0_0_offset.h | 386 #define mmUVD_POWER_STATUS 0x0004
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| vcn_2_5_offset.h | 401 #define mmUVD_POWER_STATUS 0x0004
|
