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    Searched refs:mmUVD_RBC_IB_SIZE (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h 69 #define mmUVD_RBC_IB_SIZE 0x3DA2
uvd_4_2_d.h 71 #define mmUVD_RBC_IB_SIZE 0x3da2
uvd_5_0_d.h 77 #define mmUVD_RBC_IB_SIZE 0x3da2
uvd_6_0_d.h 93 #define mmUVD_RBC_IB_SIZE 0x3da2
uvd_7_0_offset.h 196 #define mmUVD_RBC_IB_SIZE 0x05a2
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 384 #define mmUVD_RBC_IB_SIZE 0x05a2
vcn_2_0_0_offset.h 678 #define mmUVD_RBC_IB_SIZE 0x0262
vcn_2_5_offset.h 783 #define mmUVD_RBC_IB_SIZE 0x02dc
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c 523 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
amdgpu_uvd_v5_0.c 541 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
amdgpu_uvd_v6_0.c 1010 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
amdgpu_uvd_v7_0.c 1316 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));
amdgpu_vcn_v1_0.c 1519 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));

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