HomeSort by: relevance | last modified time | path
    Searched refs:mmUVD_RBC_RB_CNTL (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h 72 #define mmUVD_RBC_RB_CNTL 0x3DA9
uvd_4_2_d.h 76 #define mmUVD_RBC_RB_CNTL 0x3da9
uvd_5_0_d.h 82 #define mmUVD_RBC_RB_CNTL 0x3da9
uvd_6_0_d.h 98 #define mmUVD_RBC_RB_CNTL 0x3da9
uvd_7_0_offset.h 204 #define mmUVD_RBC_RB_CNTL 0x05a9
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c 353 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
374 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
391 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
amdgpu_uvd_v5_0.c 406 WREG32(mmUVD_RBC_RB_CNTL, tmp);
426 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
441 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
amdgpu_uvd_v7_0.c 904 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
1075 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);
1097 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
1132 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101);
amdgpu_vcn_v1_0.c 913 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
937 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1071 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1095 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
amdgpu_vcn_v2_5.c 862 WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
1042 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, tmp);
1257 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
amdgpu_uvd_v6_0.c 823 WREG32(mmUVD_RBC_RB_CNTL, tmp);
874 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
amdgpu_vcn_v2_0.c 849 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1010 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 392 #define mmUVD_RBC_RB_CNTL 0x05a9
vcn_2_0_0_offset.h 692 #define mmUVD_RBC_RB_CNTL 0x0269
vcn_2_5_offset.h 787 #define mmUVD_RBC_RB_CNTL 0x02de

Completed in 27 milliseconds