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    Searched refs:mmUVD_RBC_RB_RPTR (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h 73 #define mmUVD_RBC_RB_RPTR 0x3DA4
uvd_4_2_d.h 73 #define mmUVD_RBC_RB_RPTR 0x3da4
uvd_5_0_d.h 79 #define mmUVD_RBC_RB_RPTR 0x3da4
uvd_6_0_d.h 95 #define mmUVD_RBC_RB_RPTR 0x3da4
uvd_7_0_offset.h 198 #define mmUVD_RBC_RB_RPTR 0x05a4
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c 67 return RREG32(mmUVD_RBC_RB_RPTR);
363 WREG32(mmUVD_RBC_RB_RPTR, 0x0);
365 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
amdgpu_uvd_v5_0.c 65 return RREG32(mmUVD_RBC_RB_RPTR);
421 WREG32(mmUVD_RBC_RB_RPTR, 0);
423 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
amdgpu_vcn_v1_0.c 929 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
933 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1087 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1091 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1183 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1383 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
amdgpu_vcn_v2_0.c 865 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
869 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1019 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1021 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1059 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1248 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
amdgpu_vcn_v2_5.c 878 WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_RPTR, 0);
882 ring->wptr = RREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_RPTR);
1051 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR, 0);
1053 ring->wptr = RREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR);
1289 SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1441 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
amdgpu_uvd_v6_0.c 86 return RREG32(mmUVD_RBC_RB_RPTR);
838 WREG32(mmUVD_RBC_RB_RPTR, 0);
840 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
amdgpu_uvd_v7_0.c 82 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
1091 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);
1093 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 386 #define mmUVD_RBC_RB_RPTR 0x05a4
vcn_2_0_0_offset.h 682 #define mmUVD_RBC_RB_RPTR 0x0264
vcn_2_5_offset.h 791 #define mmUVD_RBC_RB_RPTR 0x02e0

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