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    Searched refs:mmUVD_RBC_RB_WPTR (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h 75 #define mmUVD_RBC_RB_WPTR 0x3DA5
uvd_4_2_d.h 74 #define mmUVD_RBC_RB_WPTR 0x3da5
uvd_5_0_d.h 80 #define mmUVD_RBC_RB_WPTR 0x3da5
uvd_6_0_d.h 96 #define mmUVD_RBC_RB_WPTR 0x3da5
uvd_7_0_offset.h 200 #define mmUVD_RBC_RB_WPTR 0x05a5
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c 81 return RREG32(mmUVD_RBC_RB_WPTR);
95 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
366 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
amdgpu_uvd_v5_0.c 79 return RREG32(mmUVD_RBC_RB_WPTR);
93 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
424 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
amdgpu_vcn_v1_0.c 934 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1092 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1182 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1258 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1319 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1397 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1415 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
amdgpu_vcn_v2_0.c 870 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1022 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1058 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1183 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1265 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1287 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
amdgpu_vcn_v2_5.c 883 WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR,
1054 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_WPTR,
1288 tmp = RREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1413 WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR,
1458 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
1480 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
amdgpu_uvd_v6_0.c 116 return RREG32(mmUVD_RBC_RB_WPTR);
147 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
841 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
amdgpu_uvd_v7_0.c 113 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
147 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1094 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 388 #define mmUVD_RBC_RB_WPTR 0x05a5
vcn_2_0_0_offset.h 684 #define mmUVD_RBC_RB_WPTR 0x0265
vcn_2_5_offset.h 793 #define mmUVD_RBC_RB_WPTR 0x02e1

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