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Searched refs:mmUVD_RBC_RB_WPTR_CNTL (Results 1 - 15 of 15) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h	`76 #define mmUVD_RBC_RB_WPTR_CNTL 0x3DA6`
uvd_4_2_d.h	`75 #define mmUVD_RBC_RB_WPTR_CNTL 0x3da6`
uvd_5_0_d.h	`81 #define mmUVD_RBC_RB_WPTR_CNTL 0x3da6`
uvd_6_0_d.h	`97 #define mmUVD_RBC_RB_WPTR_CNTL 0x3da6`
uvd_7_0_offset.h	`202 #define mmUVD_RBC_RB_WPTR_CNTL 0x05a6`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`390 #define mmUVD_RBC_RB_WPTR_CNTL 0x05a6`
vcn_2_0_0_offset.h	`686 #define mmUVD_RBC_RB_WPTR_CNTL 0x0266`
vcn_2_5_offset.h	`799 #define mmUVD_RBC_RB_WPTR_CNTL 0x02e6`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c	`356 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);`
amdgpu_uvd_v5_0.c	`409 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);`
amdgpu_vcn_v1_0.c	`916 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 1074 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);`
amdgpu_uvd_v6_0.c	`826 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);`
amdgpu_uvd_v7_0.c	`1078 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0);`
amdgpu_vcn_v2_0.c	`852 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);`
amdgpu_vcn_v2_5.c	`865 WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);`

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