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Searched refs:mmUVD_SOFT_RESET (Results 1 - 14 of 14) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h	`85 #define mmUVD_SOFT_RESET 0x3DA0`
uvd_4_2_d.h	`69 #define mmUVD_SOFT_RESET 0x3da0`
uvd_5_0_d.h	`75 #define mmUVD_SOFT_RESET 0x3da0`
uvd_6_0_d.h	`91 #define mmUVD_SOFT_RESET 0x3da0`
uvd_7_0_offset.h	`192 #define mmUVD_SOFT_RESET 0x05a0`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c	`313 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 315 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 317 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 334 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 337 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 434 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK \|`
amdgpu_uvd_v5_0.c	`322 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK \| 353 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 363 WREG32(mmUVD_SOFT_RESET, 0); 379 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 382 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 448 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);`
amdgpu_uvd_v7_0.c	864 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 884 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 913 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0); 978 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 1014 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 1027 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); 1044 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 1048 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, 1141 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET,
amdgpu_vcn_v1_0.c	853 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 860 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); 863 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); 879 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 883 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 1032 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); 1134 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1147 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1151 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
amdgpu_vcn_v2_0.c	`825 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect); 943 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 950 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); 953 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); 977 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 981 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 1112 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1117 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1122 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),`
amdgpu_uvd_v6_0.c	`729 WREG32(mmUVD_SOFT_RESET, 769 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 779 WREG32(mmUVD_SOFT_RESET, 0); 881 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`380 #define mmUVD_SOFT_RESET 0x05a0`
vcn_2_0_0_offset.h	`674 #define mmUVD_SOFT_RESET 0x0260`
vcn_2_5_offset.h	`493 #define mmUVD_SOFT_RESET 0x0084`

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