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    Searched refs:mmUVD_STATUS (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h 86 #define mmUVD_STATUS 0x3DAF
uvd_4_2_d.h 78 #define mmUVD_STATUS 0x3daf
uvd_5_0_d.h 84 #define mmUVD_STATUS 0x3daf
uvd_6_0_d.h 100 #define mmUVD_STATUS 0x3daf
uvd_7_0_offset.h 208 #define mmUVD_STATUS 0x05af
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c 220 if (RREG32(mmUVD_STATUS) != 0)
270 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));
324 status = RREG32(mmUVD_STATUS);
350 WREG32_P(mmUVD_STATUS, 0, ~(1<<2));
395 status = RREG32(mmUVD_STATUS);
438 WREG32(mmUVD_STATUS, 0);
amdgpu_uvd_v5_0.c 218 if (RREG32(mmUVD_STATUS) != 0)
369 status = RREG32(mmUVD_STATUS);
395 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
457 WREG32(mmUVD_STATUS, 0);
amdgpu_vcn_v1_0.c 240 RREG32_SOC15(VCN, 0, mmUVD_STATUS))
797 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
798 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
869 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
903 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
904 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
1125 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code);
1155 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1340 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1348 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE
    [all...]
amdgpu_vcn_v2_5.c 327 RREG32_SOC15(VCN, i, mmUVD_STATUS)))
911 tmp = RREG32_SOC15(UVD, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
912 WREG32_SOC15(UVD, i, mmUVD_STATUS, tmp);
994 status = RREG32_SOC15(UVD, i, mmUVD_STATUS);
1029 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0,
1159 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
1315 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
1353 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
1649 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
1663 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE
    [all...]
amdgpu_vcn_v2_0.c 247 RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
892 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
893 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
967 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
998 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1084 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
1127 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
1205 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1213 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
amdgpu_uvd_v6_0.c 545 if (RREG32(mmUVD_STATUS) != 0)
786 status = RREG32(mmUVD_STATUS);
813 WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
890 WREG32(mmUVD_STATUS, 0);
1146 (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
amdgpu_uvd_v7_0.c 807 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
897 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
919 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);
1034 status = RREG32_SOC15(UVD, k, mmUVD_STATUS);
1064 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
1469 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 396 #define mmUVD_STATUS 0x05af
vcn_2_0_0_offset.h 700 #define mmUVD_STATUS 0x026f
vcn_2_5_offset.h 489 #define mmUVD_STATUS 0x0080

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