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    Searched refs:mmUVD_VCPU_CACHE_OFFSET2 (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h 92 #define mmUVD_VCPU_CACHE_OFFSET2 0x3D3A
uvd_4_2_d.h 66 #define mmUVD_VCPU_CACHE_OFFSET2 0x3d86
uvd_5_0_d.h 72 #define mmUVD_VCPU_CACHE_OFFSET2 0x3d86
uvd_6_0_d.h 88 #define mmUVD_VCPU_CACHE_OFFSET2 0x3d86
uvd_7_0_offset.h 186 #define mmUVD_VCPU_CACHE_OFFSET2 0x0586
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 374 #define mmUVD_VCPU_CACHE_OFFSET2 0x0586
vcn_2_0_0_offset.h 624 #define mmUVD_VCPU_CACHE_OFFSET2 0x0246
vcn_2_5_offset.h 695 #define mmUVD_VCPU_CACHE_OFFSET2 0x0144
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v2_5.c 431 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, 0);
510 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
1219 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
amdgpu_uvd_v4_2.c 565 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
amdgpu_uvd_v5_0.c 282 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
amdgpu_uvd_v7_0.c 700 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
843 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
amdgpu_vcn_v1_0.c 335 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
409 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
amdgpu_vcn_v2_0.c 347 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
427 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
amdgpu_uvd_v6_0.c 608 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);

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