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    Searched refs:mmUVD_VCPU_CACHE_SIZE0 (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h 93 #define mmUVD_VCPU_CACHE_SIZE0 0x3D37
uvd_4_2_d.h 63 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83
uvd_5_0_d.h 69 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83
uvd_6_0_d.h 85 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83
uvd_7_0_offset.h 180 #define mmUVD_VCPU_CACHE_SIZE0 0x0583
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 368 #define mmUVD_VCPU_CACHE_SIZE0 0x0583
vcn_2_0_0_offset.h 618 #define mmUVD_VCPU_CACHE_SIZE0 0x0243
vcn_2_5_offset.h 689 #define mmUVD_VCPU_CACHE_SIZE0 0x0141
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v2_5.c 416 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
476 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
479 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
1192 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
amdgpu_vcn_v2_0.c 332 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
393 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
396 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
amdgpu_uvd_v4_2.c 555 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
amdgpu_uvd_v5_0.c 272 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
amdgpu_uvd_v7_0.c 687 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
830 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);
amdgpu_vcn_v1_0.c 320 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
390 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
amdgpu_uvd_v6_0.c 598 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

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