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Searched refs:mmUVD_VCPU_CACHE_SIZE1 (Results 1 - 15 of 15) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h	`94 #define mmUVD_VCPU_CACHE_SIZE1 0x3D39`
uvd_4_2_d.h	`65 #define mmUVD_VCPU_CACHE_SIZE1 0x3d85`
uvd_5_0_d.h	`71 #define mmUVD_VCPU_CACHE_SIZE1 0x3d85`
uvd_6_0_d.h	`87 #define mmUVD_VCPU_CACHE_SIZE1 0x3d85`
uvd_7_0_offset.h	`184 #define mmUVD_VCPU_CACHE_SIZE1 0x0585`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`372 #define mmUVD_VCPU_CACHE_SIZE1 0x0585`
vcn_2_0_0_offset.h	`622 #define mmUVD_VCPU_CACHE_SIZE1 0x0245`
vcn_2_5_offset.h	`693 #define mmUVD_VCPU_CACHE_SIZE1 0x0143`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v2_5.c	`424 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 500 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 1206 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),`
amdgpu_uvd_v4_2.c	`560 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);`
amdgpu_uvd_v5_0.c	`277 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);`
amdgpu_uvd_v7_0.c	`694 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE); 837 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);`
amdgpu_vcn_v1_0.c	`328 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 399 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,`
amdgpu_vcn_v2_0.c	`340 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 417 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);`
amdgpu_uvd_v6_0.c	`603 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);`

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