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    Searched refs:mmUVD_VCPU_CACHE_SIZE2 (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_d.h 95 #define mmUVD_VCPU_CACHE_SIZE2 0x3D3B
uvd_4_2_d.h 67 #define mmUVD_VCPU_CACHE_SIZE2 0x3d87
uvd_5_0_d.h 73 #define mmUVD_VCPU_CACHE_SIZE2 0x3d87
uvd_6_0_d.h 89 #define mmUVD_VCPU_CACHE_SIZE2 0x3d87
uvd_7_0_offset.h 188 #define mmUVD_VCPU_CACHE_SIZE2 0x0587
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h 376 #define mmUVD_VCPU_CACHE_SIZE2 0x0587
vcn_2_0_0_offset.h 626 #define mmUVD_VCPU_CACHE_SIZE2 0x0247
vcn_2_5_offset.h 697 #define mmUVD_VCPU_CACHE_SIZE2 0x0145
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v2_5.c 432 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
512 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
1222 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
amdgpu_uvd_v4_2.c 566 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
amdgpu_uvd_v5_0.c 283 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
amdgpu_uvd_v7_0.c 701 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2,
844 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
amdgpu_vcn_v1_0.c 336 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
410 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
amdgpu_vcn_v2_0.c 348 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
429 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
amdgpu_uvd_v6_0.c 609 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);

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