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    Searched refs:mmVGA_RENDER_CONTROL (Results 1 - 18 of 18) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vi.c 395 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
409 WREG32(mmVGA_RENDER_CONTROL,
421 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
amdgpu_gmc_v6_0.c 267 tmp = RREG32(mmVGA_RENDER_CONTROL);
269 WREG32(mmVGA_RENDER_CONTROL, tmp);
amdgpu_gmc_v7_0.c 290 tmp = RREG32(mmVGA_RENDER_CONTROL);
292 WREG32(mmVGA_RENDER_CONTROL, tmp);
amdgpu_cik.c 911 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
925 WREG32(mmVGA_RENDER_CONTROL,
937 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
amdgpu_gmc_v8_0.c 481 tmp = RREG32(mmVGA_RENDER_CONTROL);
483 WREG32(mmVGA_RENDER_CONTROL, tmp);
amdgpu_dce_v10_0.c 462 tmp = RREG32(mmVGA_RENDER_CONTROL);
467 WREG32(mmVGA_RENDER_CONTROL, tmp);
amdgpu_dce_v11_0.c 478 tmp = RREG32(mmVGA_RENDER_CONTROL);
483 WREG32(mmVGA_RENDER_CONTROL, tmp);
amdgpu_dce_v6_0.c 362 WREG32(mmVGA_RENDER_CONTROL,
363 RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL);
amdgpu_dce_v8_0.c 395 tmp = RREG32(mmVGA_RENDER_CONTROL);
400 WREG32(mmVGA_RENDER_CONTROL, tmp);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 4395 #define mmVGA_RENDER_CONTROL 0x00C0
dce_8_0_d.h 5135 #define mmVGA_RENDER_CONTROL 0xc0
dce_10_0_d.h 6018 #define mmVGA_RENDER_CONTROL 0xc0
dce_11_0_d.h 6095 #define mmVGA_RENDER_CONTROL 0xc0
dce_11_2_d.h 7769 #define mmVGA_RENDER_CONTROL 0xc0
dce_12_0_offset.h 556 #define mmVGA_RENDER_CONTROL 0x0000
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
dcn_1_0_offset.h 390 #define mmVGA_RENDER_CONTROL 0x0000
    [all...]
dcn_2_1_0_offset.h 90 #define mmVGA_RENDER_CONTROL 0x0000
    [all...]
dcn_2_0_0_offset.h 34 #define mmVGA_RENDER_CONTROL 0x0000
    [all...]

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