| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_ppatomctrl.c | 255 pp_atomctrl_memory_clock_param *mpll_param,
270 mpll_param->mpll_fb_divider.clk_frac =
272 mpll_param->mpll_fb_divider.cl_kf =
274 mpll_param->mpll_post_divider =
276 mpll_param->vco_mode =
279 mpll_param->yclk_sel =
282 mpll_param->qdr =
285 mpll_param->half_rate =
288 mpll_param->dll_speed =
290 mpll_param->bw_ctrl
[all...] |
| ppatomctrl.h | 301 extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
307 uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
309 uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_atombios.h | 168 struct atom_mpll_param *mpll_param);
|
| amdgpu_atombios.c | 1096 struct atom_mpll_param *mpll_param)
1103 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
1120 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1121 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1122 mpll_param->post_div = args.ucPostDiv;
1123 mpll_param->dll_speed = args.ucDllSpeed;
1124 mpll_param->bwcntl = args.ucBWCntl;
1125 mpll_param->vco_mode =
1127 mpll_param->yclk_sel =
1129 mpll_param->qdr
[all...] |
| amdgpu_si_dpm.c | 5358 struct atom_mpll_param mpll_param; local in function:si_populate_mclk_value
5361 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5366 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5369 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5370 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5373 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5377 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5378 YCLK_POST_DIV(mpll_param.post_div);
5408 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_iceland_smumgr.c | 1069 pp_atomctrl_memory_clock_param mpll_param; local in function:iceland_calculate_mclk_params
1073 memory_clock, &mpll_param, strobe_mode);
1078 mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
1082 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1084 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1086 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1090 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1095 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1097 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1123 if (1 == mpll_param.qdr
[all...] |
| amdgpu_ci_smumgr.c | 1045 pp_atomctrl_memory_clock_param mpll_param; local in function:ci_calculate_mclk_params
1049 memory_clock, &mpll_param, strobe_mode);
1053 mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
1056 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1058 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1060 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1063 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1067 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1069 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1080 if (1 == mpll_param.qdr
[all...] |
| amdgpu_tonga_smumgr.c | 812 pp_atomctrl_memory_clock_param mpll_param; local in function:tonga_calculate_mclk_params
816 memory_clock, &mpll_param, strobe_mode);
824 mpll_param.bw_ctrl);
829 mpll_param.mpll_fb_divider.cl_kf);
832 mpll_param.mpll_fb_divider.clk_frac);
835 mpll_param.vco_mode);
840 mpll_param.mpll_post_divider);
846 mpll_param.yclk_sel);
849 mpll_param.mpll_post_divider);
875 if (1 == mpll_param.qdr
[all...] |
| amdgpu_vegam_smumgr.c | 968 struct pp_atomctrl_memory_clock_param_ai mpll_param; local in function:vegam_calculate_mclk_params
971 clock, &mpll_param),
975 mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock;
976 mem_level->Fcw_int = (uint16_t)mpll_param.ulMclk_fcw_int;
977 mem_level->Fcw_frac = (uint16_t)mpll_param.ulMclk_fcw_frac;
978 mem_level->Postdiv = (uint8_t)mpll_param.ulPostDiv;
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_atombios.c | 2952 struct atom_mpll_param *mpll_param)
2959 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2976 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2977 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2978 mpll_param->post_div = args.ucPostDiv;
2979 mpll_param->dll_speed = args.ucDllSpeed;
2980 mpll_param->bwcntl = args.ucBWCntl;
2981 mpll_param->vco_mode =
2983 mpll_param->yclk_sel =
2985 mpll_param->qdr
[all...] |
| radeon_ci_dpm.c | 2810 struct atom_mpll_param mpll_param; local in function:ci_calculate_mclk_params
2813 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2818 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2821 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2822 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2825 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2829 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2830 YCLK_POST_DIV(mpll_param.post_div);
2839 if (mpll_param.qdr == 1
[all...] |
| radeon_si_dpm.c | 4894 struct atom_mpll_param mpll_param; local in function:si_populate_mclk_value
4897 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4902 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4905 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4906 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4909 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4913 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4914 YCLK_POST_DIV(mpll_param.post_div);
4944 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed)
[all...] |
| radeon.h | 314 struct atom_mpll_param *mpll_param);
|
