/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
amdgpu_smu7_clockpowergating.c | 170 const uint32_t *msg_id) 178 switch ((*msg_id & PP_GROUP_MASK) >> PP_GROUP_SHIFT) { 180 switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) { 182 if (PP_STATE_SUPPORT_CG & *msg_id) { 183 msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? 192 if (PP_STATE_SUPPORT_LS & *msg_id) { 193 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS 205 if (PP_STATE_SUPPORT_CG & *msg_id) { 206 msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG) ? 216 if (PP_STATE_SUPPORT_LS & *msg_id) { [all...] |
smu7_clockpowergating.h | 37 const uint32_t *msg_id);
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/src/sys/external/bsd/drm2/dist/include/drm/ |
drm_hdcp.h | 151 u8 msg_id; member in struct:hdcp2_ake_init 157 u8 msg_id; member in struct:hdcp2_ake_send_cert 164 u8 msg_id; member in struct:hdcp2_ake_no_stored_km 169 u8 msg_id; member in struct:hdcp2_ake_stored_km 174 u8 msg_id; member in struct:hdcp2_ake_send_hprime 179 u8 msg_id; member in struct:hdcp2_ake_send_pairing_info 184 u8 msg_id; member in struct:hdcp2_lc_init 189 u8 msg_id; member in struct:hdcp2_lc_send_lprime 194 u8 msg_id; member in struct:hdcp2_ske_send_eks 200 u8 msg_id; member in struct:hdcp2_rep_send_receiverid_list 208 u8 msg_id; member in struct:hdcp2_rep_send_ack 213 u8 msg_id; member in struct:hdcp2_rep_stream_manage 220 u8 msg_id; member in struct:hdcp2_rep_stream_ready [all...] |
/src/sys/external/bsd/drm2/dist/drm/amd/display/include/ |
hdcp_types.h | 92 enum hdcp_message_id msg_id; member in struct:hdcp_protection_message
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/src/usr.sbin/ldpd/ |
notifications.c | 59 t->msg_id = htonl(msg);
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tlv.h | 131 uint32_t msg_id; member in struct:notification_tlv
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/src/lib/libc/nls/ |
catgets.c | 50 _catgets(nl_catd catd, int set_id, int msg_id, const char *s) 83 r = msg_id -
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/ |
amdgpu_rv1_clk_mgr_vbios_smu.c | 76 int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param) 85 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/ |
amdgpu_rn_clk_mgr_vbios_smu.c | 61 int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param) 70 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/hdcp/ |
amdgpu_hdcp_msg.c | 137 uint8_t offset = hdcp_i2c_offsets[message_info->msg_id]; 156 if (hdcp_cmd_is_read[message_info->msg_id]) { 321 hdcp_dpcd_addrs[message_info->msg_id], 322 hdcp_cmd_is_read[message_info->msg_id]);
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/src/sys/external/bsd/drm2/dist/drm/amd/display/modules/hdcp/ |
amdgpu_hdcp_ddc.c | 150 enum mod_hdcp_ddc_message_id msg_id, 162 hdcp_dpcd_addrs[msg_id] + data_offset, 176 hdcp_i2c_offsets[msg_id], 185 enum mod_hdcp_ddc_message_id msg_id, 196 status = read(hdcp, msg_id, buf + data_offset, cur_size); 209 enum mod_hdcp_ddc_message_id msg_id, 222 hdcp_dpcd_addrs[msg_id] + data_offset, 233 hdcp->buf[0] = hdcp_i2c_offsets[msg_id];
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amdgpu_hdcp_psp.c | 45 in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE; 47 in->process.msg2_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE; 49 in->process.msg3_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE; 454 msg_in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__AKE_SEND_CERT; 501 msg_in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__AKE_SEND_H_PRIME; 508 msg_in->process.msg2_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__AKE_SEND_PAIRING_INFO; 576 msg_in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__LC_SEND_L_PRIME; 682 msg_in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_SEND_RECEIVERID_LIST; 793 msg_in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_STREAM_READY;
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hdcp_psp.h | 356 enum ta_hdcp2_msg_id msg_id; member in struct:ta_hdcp_cmd_hdcp2_authentication_message_v2
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/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
amdgpu_vi.c | 1513 uint32_t msg_id, pp_state = 0; local in function:vi_common_set_clockgating_state_by_smu 1528 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1533 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1547 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1552 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1566 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1571 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1581 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1586 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1594 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS [all...] |
amdgpu_dpm.h | 346 #define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \ 348 (adev)->powerplay.pp_handle, msg_id))
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amdgpu_gfx_v8_0.c | 5832 uint32_t msg_id, pp_state = 0; local in function:gfx_v8_0_tonga_update_gfx_clock_gating 5847 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5852 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 5869 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5874 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 5884 uint32_t msg_id, pp_state = 0; local in function:gfx_v8_0_polaris_update_gfx_clock_gating 5899 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5904 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 5919 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5924 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); [all...] |
/src/sys/dev/hyperv/ |
hypervreg.h | 185 uint64_t msg_id; member in struct:vmbus_message
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/src/sys/external/bsd/drm2/dist/drm/amd/include/ |
kgd_pp_interface.h | 281 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
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/src/sys/sys/ |
audioio.h | 321 int msg_id; member in struct:audio_mixer_name
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/src/sys/external/bsd/drm2/dist/drm/i915/display/ |
intel_hdmi.c | 1545 u8 msg_id; member in struct:hdcp2_hdmi_msg_timeout 1567 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1571 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1579 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1588 u8 msg_id, bool *msg_ready, 1603 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1614 u8 msg_id, bool paired) 1620 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1625 msg_id, &msg_ready [all...] |
intel_dp.c | 6164 u8 msg_id; member in struct:hdcp2_dp_errata_stream_type 6169 u8 msg_id; member in struct:hdcp2_dp_msg_data 6231 u8 msg_id, bool *msg_ready) 6241 switch (msg_id) { 6255 DRM_ERROR("Unidentified msg_id: %d\n", msg_id); 6268 u8 msg_id = hdcp2_msg_data->msg_id; local in function:intel_dp_hdcp2_wait_for_msg 6272 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired) 6291 msg_id, &msg_ready) [all...] |
/src/sys/dev/usb/ |
if_athn_usb.c | 1031 athn_usb_htc_msg(struct athn_usb_softc *usc, uint16_t msg_id, void *buf, 1049 msg->msg_id = htobe16(msg_id); 2087 uint16_t msg_id; local in function:athn_usb_intr 2140 msg_id = be16toh(msg->msg_id); 2141 DPRINTFN(DBG_RX, usc, "Rx HTC message %d\n", msg_id); 2142 switch (msg_id) { 2147 usc->usc_wait_msg_id, msg_id); 2148 if (usc->usc_wait_msg_id == msg_id) { [all...] |
if_athn_usb.h | 232 uint16_t msg_id; member in struct:ar_htc_msg_hdr
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/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
amdgpu_amd_powerplay.c | 301 static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id) 313 return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
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/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
hwmgr.h | 275 const uint32_t *msg_id);
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