| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_socbb.h | 70 uint32_t num_banks; member in struct:gpu_info_soc_bounding_box_v1_0
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| amdgpu_gfx.h | 128 uint8_t num_banks; member in struct:gb_addr_config
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| amdgpu_amdkfd_gfx_v10.c | 65 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
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| amdgpu_amdkfd_gfx_v7.c | 101 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
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| amdgpu_amdkfd_gfx_v8.c | 58 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
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| amdgpu_dce_v10_0.c | 1994 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v10_0_crtc_do_set_base
2000 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2002 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
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| amdgpu_dce_v11_0.c | 2036 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v11_0_crtc_do_set_base
2042 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2044 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
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| amdgpu_dce_v6_0.c | 1943 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v6_0_crtc_do_set_base
1949 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1951 fb_format |= GRPH_NUM_BANKS(num_banks);
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| amdgpu_dce_v8_0.c | 1915 unsigned bankw, bankh, mtaspect, tile_split, num_banks; local in function:dce_v8_0_crtc_do_set_base
1921 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1923 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
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| /src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| kgd_kfd_interface.h | 165 uint32_t num_banks; member in struct:tile_config
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_debug.c | 135 "plane_state->tiling_info.gfx8.num_banks = %d;\n"
146 plane_state->tiling_info.gfx8.num_banks,
227 "plane_info->tiling_info.gfx8.num_banks = %d;\n"
238 update->plane_info->tiling_info.gfx8.num_banks,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_hw_types.h | 290 unsigned int num_banks; member in struct:dc_tiling_info::__anon788fbb990708
352 unsigned int num_banks; member in struct:dc_tiling_info::__anon788fbb990808
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| kfd_crat.h | 112 uint8_t num_banks; member in struct:crat_subtype_computeunit
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| kfd_chardev.c | 1178 args->num_banks = config.num_banks;
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| kfd_crat.c | 1216 cu->num_banks = cu_info.num_shader_engines;
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| display_mode_structs.h | 101 unsigned int num_banks; member in struct:_vcs_dpi_soc_bounding_box_st
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_mem_input.c | 366 GRPH_NUM_BANKS, log_2(info->gfx9.num_banks),
379 GRPH_NUM_BANKS, info->gfx8.num_banks,
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| /src/sys/dev/pci/qat/ |
| qat.c | 1807 int num_banks; local in function:qat_crypto_init
1812 num_banks = uimin(ncpu, sc->sc_hw.qhw_num_banks);
1814 num_banks = sc->sc_ae_num;
1816 qcy->qcy_num_banks = num_banks;
1819 qat_alloc_mem(sizeof(struct qat_crypto_bank) * num_banks);
1821 for (bank = 0; bank < num_banks; bank++) {
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_atombios_crtc.c | 1285 /* Set NUM_BANKS. */
1287 unsigned index, num_banks; local in function:dce4_crtc_do_set_base
1307 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1322 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1325 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_mem_input_v.c | 177 set_reg_field_value(value, info->gfx8.num_banks,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm.c | 3263 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; local in function:fill_plane_buffer_attributes
3269 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
3272 tiling_info->gfx8.num_banks = num_banks;
3300 tiling_info->gfx9.num_banks =
3301 adev->gfx.config.gb_addr_config_fields.num_banks;
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hubp.c | 155 NUM_BANKS, log_2(info->gfx9.num_banks),
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| amdgpu_dcn10_resource.c | 131 .num_banks = 8,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_resource.c | 330 .num_banks = 8,
3398 dcn2_0_nv12_soc.num_banks =
3399 le32_to_cpu(bb->num_banks);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 265 .num_banks = 8,
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