| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu_phase.c | 61 struct sunxi_ccu_phase *phase = &clk->u.phase; local in function:sunxi_ccu_phase_get_rate
77 val = CCU_READ(sc, phase->reg);
78 delay = __SHIFTOUT(val, phase->mask);
87 struct sunxi_ccu_phase *phase = &clk->u.phase; local in function:sunxi_ccu_phase_set_rate
109 val = CCU_READ(sc, phase->reg);
110 val &= ~phase->mask;
111 val |= __SHIFTIN(delay, phase->mask);
112 CCU_WRITE(sc, phase->reg, val)
121 struct sunxi_ccu_phase *phase = &clk->u.phase; local in function:sunxi_ccu_phase_get_parent
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gem/ |
| i915_gem_pm.c | 56 }, **phase;
82 for (phase = phases; *phase; phase++) {
85 while ((obj = first_mm_object(*phase))) {
102 list_splice_tail(&keep, *phase);
|
| i915_gem_shrinker.c | 125 }, *phase;
171 for (phase = phases; phase->list; phase++) {
176 if ((shrink & phase->bit) == 0)
190 (obj = list_first_entry_or_null(phase->list,
230 list_splice_tail(&still_in_list, phase->list);
|
| /src/sys/arch/amiga/dev/ |
| sci.c | 205 int flags, phase, stat; local in function:sci_donextcmd
212 phase = DATA_IN_PHASE;
214 phase = DATA_OUT_PHASE;
216 phase = STATUS_PHASE;
223 if (phase == STATUS_PHASE || flags & XS_CTL_POLL)
225 xs->data, xs->datalen, phase);
406 int phase)
415 *dev->sci_tcmd = phase;
446 sci_ixfer_in(struct sci_softc *dev, int len, register u_char *buf, int phase)
461 *dev->sci_tcmd = phase;
508 u_char phase; local in function:sciicmd
600 u_char phase, *addr; local in function:scigo
[all...] |
| otgsc.c | 80 register u_char *buf, int phase);
82 register u_char *buf, int phase);
187 int phase)
198 *dev->sci_tcmd = phase;
233 int phase)
245 *dev->sci_tcmd = phase;
|
| wstsc.c | 80 register u_char *buf, int phase);
82 register u_char *buf, int phase);
84 register u_short *buf, int phase);
86 register u_short *buf, int phase);
205 int phase)
216 *dev->sci_tcmd = phase;
289 int phase)
301 *dev->sci_tcmd = phase;
339 int phase)
353 *dev->sci_tcmd = phase;
[all...] |
| ivsc.c | 82 register u_char *buf, int phase);
84 register u_char *buf, int phase);
194 int phase)
205 *dev->sci_tcmd = phase;
277 int phase)
289 *dev->sci_tcmd = phase;
|
| mlhsc.c | 80 register u_char *buf, int phase);
82 register u_char *buf, int phase);
180 int phase)
195 *dev->sci_tcmd = phase;
266 int phase)
282 *dev->sci_tcmd = phase;
|
| /src/sys/arch/hpcsh/hpcsh/ |
| debug.c | 46 int phase; member in struct:intr_state_rgb16
73 intr_state_rgb16->cnt = 0, intr_state_rgb16->phase ^= 1;
78 intr_state_rgb16->phase ? ~color : color;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dccg.c | 58 int modulo, phase; local in function:dccg2_update_dpp_dto
60 // phase / modulo = dpp pipe clk / dpp global clk
62 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
64 if (phase > 0xff) {
66 phase = 0xff;
70 DPPCLK0_DTO_PHASE, phase,
|
| amdgpu_dcn20_dwb_scl.c | 694 int phase; local in function:wbscl_set_scaler_filter
698 for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
700 even_coef = filter[phase * taps + 2 * pair];
702 odd_coef = filter[phase * taps + 2 * pair + 1];
708 WBSCL_COEF_RAM_PHASE, phase,
762 /* Calculate phase*/
781 /* Program phase*/
840 /* Calculate phase*/
[all...] |
| /src/sys/arch/atari/dev/ |
| ncr5380.c | 97 * device is busy internally and the first SCSI-phase will be delayed.
308 reqp->phase = NR_PHASE;
376 tmp->phase = NR_PHASE;
649 transfer_dma(reqp, reqp->phase, 0);
680 connected->phase, 0);
711 uint8_t phase; local in function:scsi_select
739 * Set phase bits to 0, otherwise the 5380 won't drive the bus during
823 * phase immediately after the selection.
885 reqp->phase = PH_CMD;
896 phase = PH_MSGOUT
967 uint8_t tmp, phase; local in function:information_transfer
1255 uint8_t phase; local in function:reselect
1664 uint8_t phase; local in function:reach_msg_out
[all...] |
| ncr5380reg.h | 99 #define SC_PHS_MTCH 0x08 /* R - Phase Match */
125 #define PH_OUT(phase) (!(phase & 1)) /* TRUE if output phase */
126 #define PH_IN(phase) (phase & 1) /* TRUE if input phase */
162 * command phase (ignoring ATN), then we flag it in the
194 uint8_t phase; /* current SCSI phase */ member in struct:req_q
[all...] |
| /src/sys/arch/mac68k/dev/ |
| ncr5380.c | 97 * device is busy internally and the first SCSI-phase will be delayed.
300 reqp->phase = NR_PHASE;
369 tmp->phase = NR_PHASE;
634 transfer_dma(reqp, reqp->phase, 0);
661 transfer_dma(connected, connected->phase, 0);
692 u_char phase; local in function:scsi_select
719 * Set phase bits to 0, otherwise the 5380 won't drive the bus during
803 * phase immediately after the selection.
865 reqp->phase = PH_CMD;
876 phase = PH_MSGOUT
946 u_char tmp, phase; local in function:information_transfer
1232 u_char phase; local in function:reselect
1629 u_char phase; local in function:reach_msg_out
[all...] |
| ncr5380reg.h | 99 #define SC_PHS_MTCH 0x08 /* R - Phase Match */
125 #define PH_OUT(phase) (!(phase & 1)) /* TRUE if output phase */
126 #define PH_IN(phase) (phase & 1) /* TRUE if input phase */
162 * command phase (ignoring ATN), then we flag it in the
194 u_char phase; /* current SCSI phase */ member in struct:req_q
[all...] |
| /src/sys/arch/hp300/stand/common/ |
| scsi.c | 210 ixfer_start(volatile struct scsidevice *hd, int len, uint8_t phase, int wait)
216 hd->scsi_pctl = phase;
271 uint8_t phase, ints; local in function:scsiicmd
280 * Wait for a phase change (or error) then let the device
284 phase = CMD_PHASE;
287 switch (phase) {
290 if (ixfer_start(hd, clen, phase, wait))
293 phase = xferphase;
300 if (ixfer_start(hd, len, phase, wait) ||
303 phase = STATUS_PHASE
[all...] |
| /src/sys/dev/isa/ |
| seagate.c | 98 * blind transfers, i.e. no check is done for scsi phase changes. This will
115 * defining SEA_NODATAOUT makes dataout phase being aborted
290 int sea_transfer_pio(struct sea_softc *sea, u_char *phase,
775 /* check for reselection phase */
875 u_char lun, phase; local in function:sea_reselect
888 /* wait for a device to win the reselection phase */
915 phase = PH_MSGIN;
916 sea_transfer_pio(sea, &phase, &len, &data);
954 phase = PH_MSGOUT;
956 sea_transfer_pio(sea, &phase, &len, &data)
1051 u_char msg[3], phase; local in function:sea_select
1148 u_char msg, phase, *msgptr; local in function:sea_abort
1259 u_char phase, tmp, old_phase = PH_INVALID; local in function:sea_information_transfer
[all...] |
| /src/tests/dev/audio/ |
| h_pad.c | 112 } phase; local in function:main
170 phase = PRE;
190 if (phase == PRE) {
197 phase = BODY;
199 } else if (phase == BODY) {
212 phase = POST;
215 } else if (phase == POST) {
|
| /src/sys/dev/ic/ |
| sunscpal.c | 56 * Gordon Ross integrated the message phase code, added lots of
125 #define ACT_CONTINUE 0x00 /* No flags: expect another phase */
195 /* This one is used when waiting for a phase change. (X100uS.) */
416 /* Ask the target for a MSG_OUT phase. */
431 sunscpal_pio_out(struct sunscpal_softc *sc, int phase, int count, uint8_t *data)
446 phase)
451 SUNSCPAL_BYTE_WRITE(sc, phase, *data++);
453 SUNSCPAL_BYTE_WRITE(sc, phase, 0);
464 sunscpal_pio_in(struct sunscpal_softc *sc, int phase, int count, uint8_t *data)
478 /* A phase change is not valid until AFTER REQ rises! *
1296 int n, phase; local in function:sunscpal_msg_in
1670 int act_flags, phase, timo; local in function:sunscpal_machine
[all...] |
| ncr5380sbc.c | 51 * Gordon Ross integrated the message phase code, added lots of
120 #define ACT_CONTINUE 0x00 /* No flags: expect another phase */
179 /* This one is used when waiting for a phase change. (X100uS.) */
226 /* Ask the target for a MSG_OUT phase. */
243 ncr5380_pio_out(struct ncr5380_softc *sc, int phase, int count, uint8_t *data)
264 if (SCI_BUS_PHASE(NCR5380_READ(sc, sci_bus_csr)) != phase)
301 ncr5380_pio_in(struct ncr5380_softc *sc, int phase, int count, uint8_t *data)
319 /* A phase change is not valid until AFTER REQ rises! */
320 if (SCI_BUS_PHASE(NCR5380_READ(sc, sci_bus_csr)) != phase)
453 * The remaining documented interrupt causes are phase mismatch an
1073 int target, lun, phase, timo; local in function:ncr5380_reselect
1558 int n, phase; local in function:ncr5380_msg_in
1798 int act_flags, n, phase, progress; local in function:ncr5380_msg_out
2175 int act_flags, phase, timo; local in function:ncr5380_machine
[all...] |
| sunscpalvar.h | 93 #define SUNSCPAL_BYTE_READ(sc, phase) (((phase) & SUNSCPAL_ICR_COMMAND_DATA) ? \
96 #define SUNSCPAL_BYTE_WRITE(sc, phase, b) do { \
97 if ((phase) & SUNSCPAL_ICR_COMMAND_DATA) { \
104 * A mask and a macro for getting the current bus phase.
112 * This illegal phase is used to prevent the PAL from having
113 * a phase-match condition when we don't want one, such as
|
| /src/sys/ufs/lfs/ |
| lfs_rfw.c | 549 kauth_cred_t cred, int phase, int *pseg_flags, struct lwp *l)
591 * Phase I: Check summary checksum.
593 if (phase == CHECK_CKSUM) {
657 if (phase == CHECK_CKSUM) {
669 if (phase == CHECK_GEN) {
676 if (phase == CHECK_INODES) {
695 if (phase == CHECK_CKSUM) {
707 if (phase == CHECK_DATA &&
723 if (phase == CHECK_CKSUM) {
735 if (phase == CHECK_CKSUM
783 int flags, dirty, phase; local in function:lfs_roll_forward
[all...] |
| /src/sys/dev/rcons/ |
| raster_text.c | 93 int phase; local in function:raster_textn
143 phase = 0;
209 rop, charrast, phase, 0 ) < 0 )
216 rop, charrast, phase, 0 ) < 0 )
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| edid.h | 114 enum gvt_gmbus_phase phase; member in struct:intel_vgpu_i2c_gmbus
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| intel-ixp42x-gateworks-gw2348.dts | 89 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
90 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
91 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
92 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
93 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
|
