Searched refs:pin (Results 1 - 25 of 704) sorted by relevance

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/src/sys/dev/pci/
H A Dppbreg.h36 * Routine to translate between secondary bus interrupt pin/device number and
37 * primary bus interrupt pin number.
39 #define PPB_INTERRUPT_SWIZZLE(pin, device) \
40 ((((pin) + (device) - 1) % 4) + 1)
/src/sys/arch/mips/alchemy/dev/
H A Daugpiovar.h47 #define AUGPIO_READ(pin) augpio_read(NULL, (pin))
48 #define AUGPIO_WRITE(pin,val) augpio_write(NULL, (pin), (val))
49 #define AUGPIO_CTL(pin,flags) augpio_ctl(NULL, (pin), (flags))
50 #define AUGPIO_GETCTL(pin) augpio_getctl(NULL, (pin))
52 #define AUGPIO2_READ(pin) augpio2_read(NULL, (pin))
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H A Daugpio.c96 int pin; local in function:augpio_attach
136 for (pin = 0; pin < sc->sc_npins; pin++) {
137 gpio_pin_t *pp = &sc->sc_pins[pin];
139 pp->pin_num = pin;
141 pp->pin_flags = sc->sc_getctl(sc, pin);
142 pp->pin_state = sc->sc_gc.gp_pin_read(sc, pin);
155 augpio_read(void *arg, int pin) argument
158 pin
167 augpio_write(void * arg,int pin,int value) argument
175 augpio_ctl(void * arg,int pin,int flags) argument
195 augpio_getctl(void * arg,int pin) argument
205 augpio2_read(void * arg,int pin) argument
217 augpio2_write(void * arg,int pin,int value) argument
232 augpio2_ctl(void * arg,int pin,int flags) argument
249 augpio2_getctl(void * arg,int pin) argument
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/src/sys/arch/evbppc/stand/wii/
H A Dgpio.c42 gpio_set(int pin) argument
44 out32(HW_GPIOB_OUT, in32(HW_GPIOB_OUT) | __BIT(pin));
48 gpio_clear(int pin) argument
50 out32(HW_GPIOB_OUT, in32(HW_GPIOB_OUT) & ~__BIT(pin));
54 gpio_get(int pin) argument
56 return (in32(HW_GPIOB_IN) >> pin) & 1;
60 gpio_enable_int(int pin) argument
62 out32(HW_GPIO_INTLVL, in32(HW_GPIO_INTLVL) | __BIT(pin));
66 gpio_disable_int(int pin) argument
68 out32(HW_GPIO_INTLVL, in32(HW_GPIO_INTLVL) & ~__BIT(pin));
72 gpio_get_int(int pin) argument
78 gpio_ack_int(int pin) argument
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/src/sys/external/gpl2/dts/dist/include/dt-bindings/pinctrl/
H A Dapple.h11 #define APPLE_PINMUX(pin, func) ((pin) | ((func) << 16))
H A Drzg2l-pinctrl.h17 * Create the pin index from its bank and position numbers and store in
22 /* Convert a port and pin label to its global pin index */
23 #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
/src/sys/dev/acpi/
H A Dqcomgpioreg.h23 #define _TLMM_GPIO_PIN_OFFSET(pin, reg) ((pin) * 0x1000 + (reg))
25 #define TLMM_GPIO_CTL(pin) _TLMM_GPIO_PIN_OFFSET(pin, 0x0)
30 #define TLMM_GPIO_IN_OUT(pin) _TLMM_GPIO_PIN_OFFSET(pin, 0x4)
34 #define TLMM_GPIO_INTR_CFG(pin) _TLMM_GPIO_PIN_OFFSET(pin, 0x8)
46 #define TLMM_GPIO_INTR_STATUS(pin) _TLMM_GPIO_PIN_OFFSET(pin,
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/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dexynos3250-pinctrl.dtsi3 * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device
17 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \
25 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; \
26 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; \
27 samsung,pin
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H A Dsama5d3_lcd.dtsi60 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
61 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
62 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
63 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
64 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
65 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
66 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
67 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
68 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
69 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
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H A Dat91sam9x5_lcd.dtsi63 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
64 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
65 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
66 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
67 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
68 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
69 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
70 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
71 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
72 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
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H A Dexynos5260-pinctrl.dtsi3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
201 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
202 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
203 samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>;
208 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
209 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
210 samsung,pin
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H A Dexynos5420-pinctrl.dtsi3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
63 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
64 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
65 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
70 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
71 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
72 samsung,pin
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H A Ds3c64xx-pinctrl.dtsi4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
136 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
137 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
142 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
143 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
148 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
149 samsung,pin
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H A Dexynos4412-pinctrl.dtsi3 * Samsung's Exynos4412 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4412 SoCs pin-mux and pin-config optiosn are listed as device
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
128 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
129 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
130 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
135 samsung,pin
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H A Ds5pv210-pinctrl.dtsi24 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
25 samsung,pin-pud-pdn = <S3C64XX_PIN_PULL_ ##_pull>; \
283 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
284 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
285 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
290 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
291 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
292 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
297 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
298 samsung,pin
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H A Dexynos4210-pinctrl.dtsi3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
10 * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
147 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
148 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
149 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
154 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
155 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
156 samsung,pin
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H A Dexynos5250-pinctrl.dtsi3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
202 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
203 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
204 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
209 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
210 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
211 samsung,pin
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H A Dexynos5410-pinctrl.dtsi3 * Exynos5410 SoC pin-mux and pin-config device tree source
282 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
283 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
284 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
289 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
290 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
291 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
296 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
297 samsung,pin
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/src/sys/arch/arm/imx/
H A Dimx23_pinctrl.c88 * Supported capabilities for each GPIO pin.
309 * Macros to map pin numbers to registers and bit fields.
312 #define PIN2MUXSEL_REG(pin) \
313 ((pin / 16) * MUXSEL_REG_SIZE + HW_PINCTRL_MUXSEL0)
314 #define PIN2MUXSEL_SET_REG(pin) \
315 ((pin / 16) * MUXSEL_REG_SIZE + HW_PINCTRL_MUXSEL0_SET)
316 #define PIN2MUXSEL_CLR_REG(pin) \
317 ((pin / 16) * MUXSEL_REG_SIZE + HW_PINCTRL_MUXSEL0_CLR)
318 #define PIN2MUXSEL_MASK(pin) (3<<(pin
530 imx23_pinctrl_gp_pin_read(void * cookie,int pin) argument
544 imx23_pinctrl_gp_pin_write(void * cookie,int pin,int value) argument
560 imx23_pinctrl_gp_pin_ctl(void * cookie,int pin,int flags) argument
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/src/sys/arch/evbsh3/ap_ms104_sh4/
H A Dap_ms104_sh4.c88 gpio_intr_establish(int pin, int (*ih_func)(void *), void *ih_arg) argument
93 KASSERT(pin >= 0 && pin <= 15);
94 KASSERT(gpio_intr_func_table[pin].ih_func == NULL);
95 KASSERT((_reg_read_4(SH4_PCTRA) & (1 << (pin * 2))) == 0); /*input*/
100 gpio_intr_func_table[pin].ih_irq = pin;
101 gpio_intr_func_table[pin].ih_func = ih_func;
102 gpio_intr_func_table[pin].ih_arg = ih_arg;
106 reg |= 1 << pin;
118 int pin = ih->ih_irq; local in function:gpior_intr_disestablish
146 int pin; local in function:gpio_intr
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/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/exynos/
H A Dexynos5433-pinctrl.dtsi3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
134 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
135 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
136 samsung,pin
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H A Dexynos7-pinctrl.dtsi3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
189 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
190 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
191 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
196 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
197 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
198 samsung,pin
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/src/sys/arch/arm/xilinx/
H A Dzynq_gpio.c48 #define MASK_DATA_REG(pin) (0x000 + 0x4 * ((pin) / 16))
49 #define DATA_RO_REG(pin) (0x060 + 0x4 * ((pin) / 32))
50 #define DATA_RO_BIT(pin) __BIT((pin) % 32)
51 #define DIRM_REG(pin) (0x204 + 0x40 * ((pin) / 32))
52 #define DIRM_BIT(pin) __BIT((pin)
93 zynq_gpio_ctl(struct zynq_gpio_softc * sc,u_int pin,int flags) argument
125 const uint8_t pin = be32toh(gpio[1]) & 0xff; local in function:zynq_gpio_acquire
151 struct zynq_gpio_pin *pin = priv; local in function:zynq_gpio_release
164 struct zynq_gpio_pin *pin = priv; local in function:zynq_gpio_read
180 struct zynq_gpio_pin *pin = priv; local in function:zynq_gpio_write
198 zynq_gpio_pin_read(void * priv,int pin) argument
213 zynq_gpio_pin_write(void * priv,int pin,int val) argument
228 zynq_gpio_pin_ctl(void * priv,int pin,int flags) argument
244 u_int pin; local in function:zynq_gpio_attach_ports
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/src/sys/dev/ic/
H A Dpl061.c51 u_int pin; local in function:plgpio_attach
61 for (pin = 0; pin < 8; pin++) {
62 sc->sc_pins[pin].pin_num = pin;
64 if ((cnf & __BIT(pin)) != 0)
66 sc->sc_pins[pin].pin_caps =
69 sc->sc_pins[pin].pin_state =
70 plgpio_pin_read(sc, pin);
84 plgpio_pin_read(void * priv,int pin) argument
94 plgpio_pin_write(void * priv,int pin,int val) argument
102 plgpio_pin_ctl(void * priv,int pin,int flags) argument
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/src/sys/arch/mips/adm5120/dev/
H A Dadmgpio.c60 admgpio_pin_ctl(void *cookie, int pin, int flags) argument
67 mask = __SHIFTIN(1 << pin, ADM5120_GPIO0_OE);
77 admgpio_pin_read(void *cookie, int pin) argument
82 KASSERT(pin >= 0 && pin < 8);
84 if (sc->sc_pins[pin].pin_flags == GPIO_PIN_INPUT)
85 mask = __SHIFTIN(1 << pin, ADM5120_GPIO0_IV);
87 mask = __SHIFTIN(1 << pin, ADM5120_GPIO0_OV);
95 admgpio_pin_write(void *cookie, int pin, int value) argument
100 KASSERT(pin >
112 int pin; local in function:admgpio_attach
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