| /src/sys/dev/pci/ |
| ppbreg.h | 36 * Routine to translate between secondary bus interrupt pin/device number and
37 * primary bus interrupt pin number.
39 #define PPB_INTERRUPT_SWIZZLE(pin, device) \
40 ((((pin) + (device) - 1) % 4) + 1)
|
| /src/sys/arch/mips/alchemy/dev/ |
| augpiovar.h | 47 #define AUGPIO_READ(pin) augpio_read(NULL, (pin))
48 #define AUGPIO_WRITE(pin,val) augpio_write(NULL, (pin), (val))
49 #define AUGPIO_CTL(pin,flags) augpio_ctl(NULL, (pin), (flags))
50 #define AUGPIO_GETCTL(pin) augpio_getctl(NULL, (pin))
52 #define AUGPIO2_READ(pin) augpio2_read(NULL, (pin))
[all...] |
| augpio.c | 96 int pin; local in function:augpio_attach
136 for (pin = 0; pin < sc->sc_npins; pin++) {
137 gpio_pin_t *pp = &sc->sc_pins[pin];
139 pp->pin_num = pin;
141 pp->pin_flags = sc->sc_getctl(sc, pin);
142 pp->pin_state = sc->sc_gc.gp_pin_read(sc, pin);
155 augpio_read(void *arg, int pin)
158 pin = 1 << pin
[all...] |
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/pinctrl/ |
| apple.h | 11 #define APPLE_PINMUX(pin, func) ((pin) | ((func) << 16))
|
| rzg2l-pinctrl.h | 17 * Create the pin index from its bank and position numbers and store in
22 /* Convert a port and pin label to its global pin index */
23 #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
|
| /src/sys/dev/acpi/ |
| qcomgpioreg.h | 23 #define _TLMM_GPIO_PIN_OFFSET(pin, reg) ((pin) * 0x1000 + (reg))
25 #define TLMM_GPIO_CTL(pin) _TLMM_GPIO_PIN_OFFSET(pin, 0x0)
30 #define TLMM_GPIO_IN_OUT(pin) _TLMM_GPIO_PIN_OFFSET(pin, 0x4)
34 #define TLMM_GPIO_INTR_CFG(pin) _TLMM_GPIO_PIN_OFFSET(pin, 0x8)
46 #define TLMM_GPIO_INTR_STATUS(pin) _TLMM_GPIO_PIN_OFFSET(pin, 0xc
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| exynos3250-pinctrl.dtsi | 3 * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device
17 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \
25 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; \
26 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; \
27 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>;
[all...] |
| sama5d3_lcd.dtsi | 60 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
61 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
62 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
63 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
64 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
65 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
66 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
67 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
68 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
69 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all...] |
| at91sam9x5_lcd.dtsi | 63 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
64 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
65 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
66 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
67 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
68 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
69 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
70 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
71 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
72 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all...] |
| exynos5260-pinctrl.dtsi | 3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
201 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
202 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
203 samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>;
208 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
209 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
210 samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>
[all...] |
| exynos5420-pinctrl.dtsi | 3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
63 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
64 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
65 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
70 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
71 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
72 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>
[all...] |
| s3c64xx-pinctrl.dtsi | 4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
16 * Pin banks
131 * Pin groups
136 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
137 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
142 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
143 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>
[all...] |
| exynos4412-pinctrl.dtsi | 3 * Samsung's Exynos4412 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4412 SoCs pin-mux and pin-config optiosn are listed as device
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
128 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
129 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
130 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
135 samsung,pin-function = <EXYNOS_PIN_FUNC_2>
[all...] |
| s5pv210-pinctrl.dtsi | 24 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
25 samsung,pin-pud-pdn = <S3C64XX_PIN_PULL_ ##_pull>; \
283 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
284 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
285 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
290 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
291 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
292 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
297 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
298 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>
[all...] |
| exynos4210-pinctrl.dtsi | 3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
10 * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
147 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
148 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
149 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
154 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
155 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
156 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>
[all...] |
| exynos5250-pinctrl.dtsi | 3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
202 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
203 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
204 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
209 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
210 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
211 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>
[all...] |
| exynos5410-pinctrl.dtsi | 3 * Exynos5410 SoC pin-mux and pin-config device tree source
282 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
283 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
284 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
289 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
290 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
291 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
296 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
297 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>
[all...] |
| /src/sys/arch/arm/imx/ |
| imx23_pinctrl.c | 88 * Supported capabilities for each GPIO pin.
94 /* PIN 0 */
96 /* PIN 1 */
98 /* PIN 2 */
100 /* PIN 3 */
102 /* PIN 4 */
104 /* PIN 5 */
106 /* PIN 6 */
108 /* PIN 7 */
110 /* PIN 8 *
[all...] |
| /src/sys/arch/evbsh3/ap_ms104_sh4/ |
| ap_ms104_sh4.c | 88 gpio_intr_establish(int pin, int (*ih_func)(void *), void *ih_arg)
93 KASSERT(pin >= 0 && pin <= 15);
94 KASSERT(gpio_intr_func_table[pin].ih_func == NULL);
95 KASSERT((_reg_read_4(SH4_PCTRA) & (1 << (pin * 2))) == 0); /*input*/
100 gpio_intr_func_table[pin].ih_irq = pin;
101 gpio_intr_func_table[pin].ih_func = ih_func;
102 gpio_intr_func_table[pin].ih_arg = ih_arg;
106 reg |= 1 << pin;
118 int pin = ih->ih_irq; local in function:gpior_intr_disestablish
146 int pin; local in function:gpio_intr
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/exynos/ |
| exynos5433-pinctrl.dtsi | 3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
14 #define PIN(_func, _pin, _pull, _drv) \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
134 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
135 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>
[all...] |
| exynos7-pinctrl.dtsi | 3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
189 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
190 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
191 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
196 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
197 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
198 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>
[all...] |
| /src/sys/arch/arm/xilinx/ |
| zynq_gpio.c | 48 #define MASK_DATA_REG(pin) (0x000 + 0x4 * ((pin) / 16))
49 #define DATA_RO_REG(pin) (0x060 + 0x4 * ((pin) / 32))
50 #define DATA_RO_BIT(pin) __BIT((pin) % 32)
51 #define DIRM_REG(pin) (0x204 + 0x40 * ((pin) / 32))
52 #define DIRM_BIT(pin) __BIT((pin) % 32
125 const uint8_t pin = be32toh(gpio[1]) & 0xff; local in function:zynq_gpio_acquire
151 struct zynq_gpio_pin *pin = priv; local in function:zynq_gpio_release
164 struct zynq_gpio_pin *pin = priv; local in function:zynq_gpio_read
180 struct zynq_gpio_pin *pin = priv; local in function:zynq_gpio_write
244 u_int pin; local in function:zynq_gpio_attach_ports
[all...] |
| /src/sys/dev/ic/ |
| pl061.c | 51 u_int pin; local in function:plgpio_attach
61 for (pin = 0; pin < 8; pin++) {
62 sc->sc_pins[pin].pin_num = pin;
64 if ((cnf & __BIT(pin)) != 0)
66 sc->sc_pins[pin].pin_caps =
69 sc->sc_pins[pin].pin_state =
70 plgpio_pin_read(sc, pin);
[all...] |
| /src/sys/arch/mips/adm5120/dev/ |
| admgpio.c | 60 admgpio_pin_ctl(void *cookie, int pin, int flags)
67 mask = __SHIFTIN(1 << pin, ADM5120_GPIO0_OE);
77 admgpio_pin_read(void *cookie, int pin)
82 KASSERT(pin >= 0 && pin < 8);
84 if (sc->sc_pins[pin].pin_flags == GPIO_PIN_INPUT)
85 mask = __SHIFTIN(1 << pin, ADM5120_GPIO0_IV);
87 mask = __SHIFTIN(1 << pin, ADM5120_GPIO0_OV);
95 admgpio_pin_write(void *cookie, int pin, int value)
100 KASSERT(pin >= 0 && pin < 8)
112 int pin; local in function:admgpio_attach
[all...] |
| /src/sys/dev/ppbus/ |
| ppbus_gpio.c | 81 gpio_pin_t *pin; local in function:gpio_ppbus_attach
84 for (pin = &sc->sc_gpio_pins[0], i = 0; i < PPBUS_NPINS; pin++, i++) {
85 pin->pin_num = i;
88 pin->pin_caps = GPIO_PIN_INPUT;
89 pin->pin_flags = GPIO_PIN_INPUT;
90 pin->pin_state = gpio_ppbus_pin_read(sc, i);
92 pin->pin_caps = GPIO_PIN_OUTPUT;
93 pin->pin_flags = GPIO_PIN_OUTPUT;
94 pin->pin_state = GPIO_PIN_LOW
[all...] |
